Datasheet CAP400DG (Power Integrations) - 3

CAP400DG PCB Layout and External Resistor Selection
Figure 5 shows a typical layout to use with a CAP400DG IC. The discharge resistance is provided by R1 and R2 which share the discharge energy, distributing losses during fault conditions (such as a short between D1 and D2). Resistors R1 and R2 are each rated for 50% of the system input voltage to ensure safe operation during X Capacitor single fault testing. If lower dissipation or lower voltage across each R1 resistor is required during fault tests, the total external resistance can be divided between additional resistors.
Safety
The CAPZero™-4 IC meets safety requirements even if placed before the system input fuse. If a short-circuit occurs between D1 and D2, the system behaves in the same way as conventional passive discharge circuits. It is not possible to create an open circuit fault condition through a R2 single pin fault (such as created during the lifted-pin test) since two ≥4 mm pins are connected to D1 and and two to D2. If multiple disconnected pins create an open circuit, the condition is identical to an open circuit X capacitor discharge resistor in existing systems where CAP400DG is not used. If redundancy against open circuit faults is required, two CAP400DG ICs and R1 / R2 circuits can be placed in paral el. PI-5610-020515 Figure 5. Typical PCB Layout.
3 PRELIMINARY
Rev. A 06/26 www.power.com