Datasheet CH32X033, CH32X035 (Nanjing Qinheng Microelectronics) - 10

CH32X035 Datasheet https://wch-ic.com multi-master mode, full-duplex or half-duplex synchronous transmission, support basic SD card and MMC mode. Programmable clock polarity and phase, data bit width provides 8 or 16-bit selection, hardware CRC generation/check for reliable communication, and continuous communication support for DMA operation.
1.4.16 I2C Bus
The chip provides one I2C bus interface, capable of working in multi-master or slave mode, performing all I2C bus specific timing, protocols, arbitration, etc. Both standard and fast communication speeds are supported. The I2C interface provides 7-bit or 10-bit addressing, and supports dual slave addressing in 7-bit Slave mode. It integrates built-in hardware CRC generator/checker. It also supports DMA operation. Note: The I2C function is not applicable to products whose lot number ends with 0 as the fifth-to-last digit.
1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS)
USB2.0 Full-speed Host Controller and Device Controller (USBFS) following the USB2.0 Fullspeed standard and supporting the BC charging protocol. Provides 8 configurable USB device endpoints and a set of host endpoints. Supports control/bulk/isochronous/interrupt transfer, double buffer mechanism, USB bus suspend/resume operation, and provides standby/wake-up function. The 48MHz clock dedicated to the USBFS module is generated directly from the internal high-speed clock (HSI).
1.4.18 USB PD and Type-C Controller (USB PD)
Built-in USB Power Delivery controller and PD transceiver PHY, support USB Type-C master-slave detection, automatic BMC codec and CRC, hardware edge control, support USB PD2.0 and PD3.0 power delivery control, support fast charging, support UFP/PD powered end Sink and DFP/PD powered end Source applications and DRP applications, supports PDUSB. The CH211 Type-C/PD high-voltage interface chip additionally enables 28V direct power supply, internal boost pump control of N-channel MOSFETs, 28V tolerant voltage on the CC pin, and an integrated 5KΩ controlled pull- down resistor compliant with Type-C specifications.
1.4.19 General-purpose Input and Output (GPIO)
The system provides 3 groups of GPIO ports with a total of 60 GPIO pins. Each pin can be configured by software as an output, input (with or without pull-up, some pins support pull-down) or multiplexed peripheral function port. All GPIO pins support controlled pull-up, only PA0-PA15 and PC16-PC17 support controlled pull-down, the remaining pins do not support pull-down. PC14-PC17 support multiple pull-up modes, set by dedicated control registers corresponding to the PD and USB pins respectively. Most GPIO pins are shared with either digital or analogue multiplexed peripherals. All PA and PB GPIO pins have high current drive capability with simple constant current functionality and all support PWM. a lockout mechanism is provided to freeze the I/O configuration to avoid accidental writes to I/O registers. Most of the I/O pins in the system are powered by VDD, and changing the VDD power supply will change the I/O pin output level high enough to adapt to the external communication interface level. Please refer to the pin description for specific pins. V2.3 8 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules