Datasheet CH32X033, CH32X035 (Nanjing Qinheng Microelectronics) - 3

CH32X035 Datasheet https://wch-ic.com
Chapter 1 Specification Information 1.1 System Structure
The microcontroller is designed on the basis of the RISC-V instruction set, and its architecture integrates the QingKe microprocessor core, arbitration unit, DMA module, SRAM storage and other components through multiple bus groups to achieve interaction. A general-purpose DMA controller is integrated to reduce the CPU load and improve access efficiency, and a multi-level clock management mechanism is applied to reduce the power consumption of peripherals. The following diagram shows the overall internal architecture of the series chip. Figure 1-1 System Block Diagram @VDD VDD: 2V~5.5V RISC-V (V4C) FLASH I-code Bus GND CTRL POR PDR PVD PFIC RV32 SWCLK IMAC SDI D-code Bus SWDIO Flash X U Memory M DMA Channels Bus System SYSCLK X Reset & U HBCLK SRAM M MUX & DIV HSI_DIV6_CLK HSI_47KHZ_CLK DP DM USBFS HSI-RC RCC CC1、CC2 AWU_CLK USBPD IWDG_CLK N0、N1、N2 P0、P1、P2 OPA1 OUT0、OUT1 4 channels N0、N1、N2 TIM2 3 complementary Channels P0、P1、P2 OPA2 ETR, BIKN OUT0、OUT1 TIM3 2 channels N0、N1 P0、P1 CMP1 OUT USART2 RX, TX, CTS, RTS,CK N0、N1 P0、P1 CMP2 USART3 RX, TX, CTS, RTS,CK
H
OUT
B
USART4 N0、N1 RX, TX, CTS, RTS,CK P0、P1 CMP3 OUT IWDG PA0 ~ PA23 GPIOA WWDG PB0 ~ PB21 GPIOB I2C SCL, SDA PC0 ~ PC7 GPIOC PC14 ~ PC19 PWR MOSI,MISO,SCK, NSS SPI PIOC RX, TX, CTS, RTS,CK USART1 AWU 4 channels 3 complementary Channels TIM1 ETR, BIKN AFIO AIN0 ~ AIN13 Tkey EXTI (GND)VREF - ADC VREF+ V2.3 1 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules