Datasheet GD32E103xx (GigaDevice) - 10
| Hersteller | GigaDevice |
| Beschreibung | Arm Cortex-M4 32-bit MCU |
| Seiten / Seite | 91 / 10 — 2.2. Block diagram. Figure 2-1.GD32E103xx block diagram |
| Revision | 1.15 |
| Dateiformat / Größe | PDF / 3.1 Mb |
| Dokumentensprache | Englisch |
2.2. Block diagram. Figure 2-1.GD32E103xx block diagram
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GD32E103xx Datasheet
2.2. Block diagram Figure 2-1.GD32E103xx block diagram
TPIU SW/JTAG POR/ PDR IC o d Flash e Flash Ibus ARM Cortex-M4 Memory PLL D Memory Processor C Control er Fmax : 120MHz o Dbus Fmax:120MHz d e S LDO y FMC USBFS CRC RCU s t 1.2V e NVIC m Master Slave AHB Peripherals A H IRC B DMA 12 chs M SRAM 8MHz SRAM Master a Control er tr Slave ix HXTAL AHB to APB AHB to APB 4-32MHz Slave Bridge 2 Bridge 1 EXMC Slave LVD Interrput request Powered By VDDA USART0 Slave Slave SPI0 WWDGT 12-bit TIMER1~3 ADC0~1 SAR ADC Powered By VDDA EXTI SPI1~2 GPIOA USART1~2 GPIOB APB I2C0 APB 2 : 1 : F I2C1 GPIOC m F a m x a x = = FWDGT GPIOD 120 60 M M H H RTC GPIOE z Z DAC0 TIMER4~6 TIMER0 UART3~4 TIMER7 TIMER 11~13 TIMER8~10 CTC 9 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E103Vx LQFP100 pin definitions 2.6.2. GD32E103Rx LQFP64 pin definitions 2.6.3. GD32E103Cx LQFP48 pin definitions 2.6.4. GD32E103Tx QFN36 pin definitions 3. Functional description 3.1. Arm® Cortex®-M4 core 3.2. On-chip memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus full-speed interface (USBFS) 3.17. External memory controller (EXMC) 3.18. Debug mode 3.19. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. ADC characteristics 4.14. Temperature sensor characteristics 4.15. DAC characteristics 4.16. I2C characteristics 4.17. SPI characteristics 4.18. I2S characteristics 4.19. USART characteristics 4.20. USBFS characteristics 4.21. EXMC characteristics 4.22. TIMER characteristics 4.23. WDGT characteristics 4.24. Parameter conditions 5. Package information 5.1. LQFP100 package outline dimensions 5.2. LQFP64 package outline dimensions 5.3. LQFP48 package outline dimensions 5.4. QFN36 package outline dimensions 5.5. Thermal characteristics 6. Ordering information 7. Revision history
2.2. Block diagram Figure 2-1.GD32E103xx block diagram
TPIU SW/JTAG POR/ PDR IC o d Flash e Flash Ibus ARM Cortex-M4 Memory PLL D Memory Processor C Control er Fmax : 120MHz o Dbus Fmax:120MHz d e S LDO y FMC USBFS CRC RCU s t 1.2V e NVIC m Master Slave AHB Peripherals A H IRC B DMA 12 chs M SRAM 8MHz SRAM Master a Control er tr Slave ix HXTAL AHB to APB AHB to APB 4-32MHz Slave Bridge 2 Bridge 1 EXMC Slave LVD Interrput request Powered By VDDA USART0 Slave Slave SPI0 WWDGT 12-bit TIMER1~3 ADC0~1 SAR ADC Powered By VDDA EXTI SPI1~2 GPIOA USART1~2 GPIOB APB I2C0 APB 2 : 1 : F I2C1 GPIOC m F a m x a x = = FWDGT GPIOD 120 60 M M H H RTC GPIOE z Z DAC0 TIMER4~6 TIMER0 UART3~4 TIMER7 TIMER 11~13 TIMER8~10 CTC 9 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E103Vx LQFP100 pin definitions 2.6.2. GD32E103Rx LQFP64 pin definitions 2.6.3. GD32E103Cx LQFP48 pin definitions 2.6.4. GD32E103Tx QFN36 pin definitions 3. Functional description 3.1. Arm® Cortex®-M4 core 3.2. On-chip memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus full-speed interface (USBFS) 3.17. External memory controller (EXMC) 3.18. Debug mode 3.19. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. ADC characteristics 4.14. Temperature sensor characteristics 4.15. DAC characteristics 4.16. I2C characteristics 4.17. SPI characteristics 4.18. I2S characteristics 4.19. USART characteristics 4.20. USBFS characteristics 4.21. EXMC characteristics 4.22. TIMER characteristics 4.23. WDGT characteristics 4.24. Parameter conditions 5. Package information 5.1. LQFP100 package outline dimensions 5.2. LQFP64 package outline dimensions 5.3. LQFP48 package outline dimensions 5.4. QFN36 package outline dimensions 5.5. Thermal characteristics 6. Ordering information 7. Revision history