Datasheet KSZ8794CNX (Microchip) - 27

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KSZ8794CNX
3.5.1.2 MII Management Interface (MIIM) The KSZ8794CNX supports the standard IEEE 802.3 MII management interface, also known as the management data input/output (MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8794CNX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY set- tings. Further details on the MIIM interface are found in the IEEE 802.3u Specification. The MIIM interface consists of the following: • A physical connection that incorporates the data line MDIO and the clock line MDC. • A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8794CNX device. • Access to a set of eight 16-bit registers, consisting of 8 standard MIIM Registers [0:5h], 1d and 1f MIIM registers per port. The MIIM interface MDC/MDIO can operate up to a maximum clock speed of 25 MHz MDC clock. Table 3-6 depicts the MII management interface frame format.
TABLE 3-6: MII MANAGEMENT INTERFACE FRAME FORMAT Read/ PHY REG Start of Preamble Write Address Address TA Data Bits[15:0] Idle Frame OP Code Bits[4:0] Bits[4:0] Read
32 1s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write
32 1s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z The MIIM interface does not have access to all the configuration registers in the KSZ8794CNX. It can only access the standard MIIM register (see the MIIM Registers section). The SPI interface, on the other hand, can be used to access all registers with the entire KSZ8794CNX feature set. 3.5.2 SWITCH PORT 4 GMAC INTERFACE The KSZ8794CNX GMAC4 interface supports the MII/RGMII/RMII four interfaces protocols and shares one set of input/ output signals. The purpose of this interface is to provide a simple, inexpensive, and easy-to implement interconnection between the GMAC/MAC sub layer and a GPHY/PHY. Data on these interfaces are framed using the IEEE Ethernet standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC) checksum. Transmit and receive signals for MII/RGMII/RMII interfaces shown in Table 3-7.
TABLE 3-7: SIGNALS OF RGMII/MII/RMII Direction Type RGMII MII RMII
Input (Output) GTXC TXC REFCLKI Input — TXER — Input TXD_CTL TXEN TXEN Input (Output) — COL — Input TXD[3:0] TXD[3:0] TXD[1:0] Input (Output) GRXC RXC RXC Output — RXER RXER Output RXD_CTL RXDV CRS_DV Input (Output) — CRS — Output RXD[3:0] RXD[3:0] RXD[1:0] 3.5.2.1 Standard Media Independent Interface (MII) The MII is capable of supporting 10/100 Mbps operation. Data and delimiters are synchronous to clock references. It provides independent four transmit and receive data paths and uses signal levels, two media status signals are pro- vided. The CRS indicates the presence of carrier, and the COL indicates the occurrence of a collision. Both half- and full-duplex operations are provided by the MII.  2016 Microchip Technology Inc. DS00002134A-page 27 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines