Datasheet KSZ8794CNX (Microchip) - 9

KSZ8794CNX TABLE 2-1: SIGNALS - KSZ8794CNX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
45 COL4 Ipd/O 4 MII: Port 4 Switch MII col ision detects. RGMII/RMII: No connection. 46 REFCLKO Ipu/O — 25 MHz Clock Output (Option) Controlled by the strap pin LED2_0. Default is enabled, it is better to disable it if it’s not being used. 47 PME_N I/O — Power Management Event This output signal indicates that a Wake On LAN event has been detected as a result of a Wake-Up frame being detected. The KSZ8794CNX is requesting the system to wake up from low power mode. Its assertion polarity is programmable with the default polarity to be active low. 48 LED2_1 Ipu/O 2 Port 2 LED Indicator 1 See Global Register 11 bits [5:4] for details. Strap Option: Port 4 MII and RMII Modes Select When Port 4 is MII mode: PU = MAC mode. PD = PHY mode. When Port 4 is RMII mode: PU = Clock mode in RMII, using 25 MHz OSC clock and provide 50 MHz RMII clock from pin RXC4. PD = Normal mode in RMII, the TXC4/REFCLKI4 pin on the Port 4 RMII will receive an external 50 MHz clock.
Note:
Port 4 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit [7]. 49 LED2_0 Ipu/O 2 Port 2 LED Indicator 0 See Global Register 11 bits [5:4] for details. Strap Option: REFCLKO Enable PU = REFCLK_O (25 MHz) is enabled. (Default) PD = REFCLK_O is disabled
Note:
It is better to disable this 25 MHz clock if not providing an extra 25 MHz clock for system. 50 LED1_1 Ipu/O 1 Port 1 LED Indicator 1. See Global Register 11 bits [5:4] for details. Strap Option: PLL Clock Source Select PU = Still use 25 MHz clock from XI/XO pin even though it is in Port 4 RMII normal mode. PD = Use external clock from TXC4 in Port 4 RMII normal mode.
Note:
If received clock in Port 4 RMII normal mode has bigger clock jitter, one can still select the 25 MHz Crystal/Oscillator as switch’s clock source. 51 LED1_0 Ipu/O 1 Port 1 LED Indicator 0 See Global Register 11 bits [5:4] for details. Strap Option: Speed Select in RGMII PU = 1 Gbps in RGMII. (Default) PD = 10/100 Mbps in RGMII.
Note:
Programmable through internal registers also.  2016 Microchip Technology Inc.

DS00002134A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines