Datasheet KSZ8794CNX (Microchip) - 8
| Hersteller | Microchip |
| Beschreibung | Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface |
| Seiten / Seite | 124 / 8 — KSZ8794CNX. TABLE 2-1:. SIGNALS - KSZ8794CNX (CONTINUED). Pin. Type. … |
| Dateiformat / Größe | PDF / 1.7 Mb |
| Dokumentensprache | Englisch |
KSZ8794CNX. TABLE 2-1:. SIGNALS - KSZ8794CNX (CONTINUED). Pin. Type. Port. Description. Number. Name. Note 2-1
Modelllinie für dieses Datenblatt
Textversion des Dokuments
KSZ8794CNX TABLE 2-1: SIGNALS - KSZ8794CNX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
25 TXD4_1 Ipd 4 RGMII/MII/RMII: Port 4 Switch transmit bit [1]. 26 GNDD GND — Digital Ground. 27 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 28 TXD4_2 Ipd 4 RGMII/MII: Port 4 Switch transmit bit [2]. RMII: No connection. 29 TXD4_3 Ipd 4 RGMII/MII: Port 4 Switch transmit bit [3]. RMII: No connection. 30 TXER4 Ipd 4 MII: Port 4 Switch transmit error. RGMII/RMII: No connection. 31 NC NC — No Connect. 32 GNDD GND — Digital Ground. 33 VDD12D P — 1.2V Core Power. 34 TXC4/ I/O 4 Port 4 Switch GMAC4 Clock Pin REFCLKI4 MII: 2.5/25 MHz clock, PHY mode is output, MAC mode is input. /GTXC4 RMII: Input for receiving 50 MHz clock in normal mode RGMII: Input 125 MHz clock with falling and rising edge to latch data for the transmit. 35 RXC4/ I/O 4 Port 4 Switch GMAC4 Clock Pin GRXC4 MII: 2.5/25 MHz clock, PHY mode is output, MAC mode is input. RMII: Output 50 MHz reference clock for the receiving/transmit in the clock mode. RGMII: Output 125 MHz clock with falling and rising edge to latch data for the receiving. 36 RXD4_0 Ipd/O 4 RGMII/MII/RMII: Port 4 Switch receive bit [0]. 37 RXD4_1 Ipd/O 4 RGMII/MII/RMII: Port 4 Switch receive bit [1]. 38 GNDD GND — Digital Ground. 39 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 40 RXD4_2 Ipd/O 4 RGMII/MII: Port 4 Switch receive bit [2]. RMII: No connection. 41 RXD4_3 Ipd/O 4 RGMII/MII: Port 4 Switch receive bit [3]. RMII: No connection. 42 RXDV4/ Ipd/O 4 MII: RXDV4 is for Port 4 Switch GMII/MII receive data valid. CRSDV4 RMII: CRSDV4 is for Port 4 RMII carrier sense/receive data /RXD4_CTL valid output. RGMII: RXD4_CTL is for Port 4 RGMII receive data control 43 RXER Ipd/O 4 MII: Port 4 Switch receives error. RGMII/RMII: No connection. 44 CRS4 Ipd/O 4 MII: Port 4 Switch MII modes carrier sense. RGMII/RMII: No connection. DS00002134A-page 8
2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
25 TXD4_1 Ipd 4 RGMII/MII/RMII: Port 4 Switch transmit bit [1]. 26 GNDD GND — Digital Ground. 27 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 28 TXD4_2 Ipd 4 RGMII/MII: Port 4 Switch transmit bit [2]. RMII: No connection. 29 TXD4_3 Ipd 4 RGMII/MII: Port 4 Switch transmit bit [3]. RMII: No connection. 30 TXER4 Ipd 4 MII: Port 4 Switch transmit error. RGMII/RMII: No connection. 31 NC NC — No Connect. 32 GNDD GND — Digital Ground. 33 VDD12D P — 1.2V Core Power. 34 TXC4/ I/O 4 Port 4 Switch GMAC4 Clock Pin REFCLKI4 MII: 2.5/25 MHz clock, PHY mode is output, MAC mode is input. /GTXC4 RMII: Input for receiving 50 MHz clock in normal mode RGMII: Input 125 MHz clock with falling and rising edge to latch data for the transmit. 35 RXC4/ I/O 4 Port 4 Switch GMAC4 Clock Pin GRXC4 MII: 2.5/25 MHz clock, PHY mode is output, MAC mode is input. RMII: Output 50 MHz reference clock for the receiving/transmit in the clock mode. RGMII: Output 125 MHz clock with falling and rising edge to latch data for the receiving. 36 RXD4_0 Ipd/O 4 RGMII/MII/RMII: Port 4 Switch receive bit [0]. 37 RXD4_1 Ipd/O 4 RGMII/MII/RMII: Port 4 Switch receive bit [1]. 38 GNDD GND — Digital Ground. 39 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 40 RXD4_2 Ipd/O 4 RGMII/MII: Port 4 Switch receive bit [2]. RMII: No connection. 41 RXD4_3 Ipd/O 4 RGMII/MII: Port 4 Switch receive bit [3]. RMII: No connection. 42 RXDV4/ Ipd/O 4 MII: RXDV4 is for Port 4 Switch GMII/MII receive data valid. CRSDV4 RMII: CRSDV4 is for Port 4 RMII carrier sense/receive data /RXD4_CTL valid output. RGMII: RXD4_CTL is for Port 4 RGMII receive data control 43 RXER Ipd/O 4 MII: Port 4 Switch receives error. RGMII/RMII: No connection. 44 CRS4 Ipd/O 4 MII: Port 4 Switch MII modes carrier sense. RGMII/RMII: No connection. DS00002134A-page 8
2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines