Datasheet RX74M (Renesas) - 9

RX74M Group 1. Overview
Table 1.1 Outline of Specifications (8/10) Classification Module/Function Description
Communications CAN FD module with 2 channels functions gateway functionality Compliance with the ISO11898-1:2015 specification (standard frame and extended (CANFDG) frame) Gateway function Message buffers 32 receive message buffers 16 transmit message buffers per channel Four transmit queues per channel FIFO Eight receive FIFOs Six common FIFOs CAN FD module 1 channel (CANFD) Compliance with the ISO11898-1:2015 specification (standard frame and extended frame) Message buffers 16 receive message buffers Four transmit message buffers One transmit queue FIFO Tow receive FIFOs One common FIFO Serial peripheral 3 channels interface (RSPIA) RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Transmit/receive data can be swapped in byte units Buffered structure The transmitter and receiver each have four-stage 32-bit FIFO buffers to enable continuous transmission and reception. RSPCK can be stopped with the receive buffer full for master reception. Event linking by the ELC Communications protocol: RSPIA supports the Texas Instruments Synchronous Serial Protocol (TI SSP). Expanded serial 2 units (switchable between controller and target) peripheral interface Compliant with xSPI (JEDEC Standards JESD 251, JESD 251-1, and JESD 252) (XSPI) 1-bit, 2-bit, 4-bit, and 8-bit protocols supported Supports Octal SPI in the JESD 251 Profile 1.0, and HyperBusTM (HyperRAMTM and HyperFlashTM) in the JESD 251 Profile 2.0. Supports decryption on the fly (DOTF) Maximum operating rate as a controller: 266 MT/s (133-MHz clock) Maximum operating rate as a target: 200 MT/s (100-MHz clock) Serial sound interface (SSIE) 2 channels Full-duplex transmission (for both channel 0 and channel 1) Various types of serial audio formatting are supported. Master and slave operations are supported. The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8, 1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128). Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported. 32-stage FIFO buffers for transmission and reception Stopping or not stopping the SSILRCK signal on stopping of data transmission is selectable. Clock signal from a GPTW is selectable. R01DS0433EJ0110 Rev.1.10 Page 9 of 299 Jul 31, 2026 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 1.5.1 320-Pin LFBGA 1.5.2 224-Pin LFBGA 1.5.3 176-Pin LFBGA 1.5.4 176-Pin LFQFP 1.5.5 144-Pin LFQFP 1.5.6 100-Pin LFQFP 1.6 List of Pin and Pin Functions 1.6.1 320-Pin LFBGA 1.6.2 224-Pin LFBGA 1.6.3 176-Pin LFBGA 1.6.4 176-Pin LFQFP 1.6.5 144-Pin LFQFP 1.6.6 100-Pin LFQFP 2. Electrical Characteristics 2.1 Test Conditions 2.1.1 Maximum and Minimum Values (Max./Min.) 2.1.2 Typical Values (Typ.) 2.2 Absolute Maximum Ratings 2.3 Recommended Operating Conditions 2.4 DC Characteristics 2.4.1 Characteristics of the Input Voltage of the I/O Pins 2.4.2 Characteristics of the Output Voltage of the I/O Pins 2.4.3 Characteristics of the Other I/O Pins 2.4.4 Operating and Standby Currents 2.4.4.1 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = A, B, C, D, T, U, V, W) 2.4.4.2 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = E, F) 2.4.4.3 Currents in Deep Software Standby Mode 2.4.4.4 Other Operating Currents 2.4.4.5 Permissible Output Currents 2.4.5 Thermal Characteristics 2.4.5.1 Thermal Resistance Value 2.4.5.2 Supply Currents for the Peripheral Functions 2.4.5.3 Example of Calculation of Ta 2.4.6 VCC Rising and Falling Slopes and Ripple Frequency 2.5 AC Characteristics 2.5.1 Operating Frequency 2.5.2 Clock Timing 2.5.3 Reset Timing 2.5.4 Timing of Return from Low Power Consumption Modes 2.5.5 Control Signal Timing 2.5.6 Bus Timing 2.5.7 Timing of On-Chip Peripheral Modules 2.5.7.1 I/O Port 2.5.7.2 TMR 2.5.7.3 CMTW 2.5.7.4 POEG 2.5.7.5 GPTW 2.5.7.6 RSCI 2.5.7.7 RSPIA 2.5.7.8 XSPI 2.5.7.9 RIICHS 2.5.7.10 RI3C 2.5.7.11 SSIE 2.5.7.12 SD/MMC Host Interface 2.5.7.13 PDC 2.5.7.14 HRPWM 2.5.7.15 CANFD/CANFDG 2.5.7.16 ESC 2.5.7.17 ESWM 2.5.7.18 PDMIF 2.5.7.19 Δ-Σ Interface 2.5.7.20 PCIF 2.5.7.21 PIO 2.5.7.22 A/D Converter Trigger 2.5.7.23 CAC 2.6 USB Characteristics 2.6.1 USB Timing 2.6.2 USBHS Timing 2.7 A/D Conversion Characteristics 2.7.1 Analog Input Voltage Range 2.7.2 Common Characteristics of the 16-Bit A/D Converter 2.7.3 SAR Mode Characteristics 2.7.4 Common Characteristics of Oversampling Mode and Hybrid Mode 2.7.5 Oversampling Mode Characteristics 2.7.6 Hybrid Mode Characteristics 2.8 D/A Conversion Characteristics 2.9 Temperature Sensor Characteristics 2.10 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 2.11 Core Voltage Monitoring Reset Characteristics 2.12 Oscillation Stop Detection Timing 2.13 External VDD Timing Characteristics 2.14 Battery Backup Function Characteristics 2.15 MRAM Characteristics 2.15.1 Code MRAM Characteristics 2.15.2 Option-Setting Memory (MRAM Area) Characteristics 2.15.3 Option-Setting Memory (OTP Area with ECC) Characteristics 2.15.4 Option-Setting Memory (OTP Area without ECC) Characteristics 2.15.5 MACI Command Characteristics 2.15.6 W-HUK Zeroization Characteristics 2.15.7 MRAM Magnetic Field Resistance Characteristics 2.15.8 Data MRAM Characteristics 2.16 Boundary Scan 2.17 Usage Note 2.17.1 Connecting VCL Capacitor and Bypass Capacitors Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice