Datasheet RX74M (Renesas) - 3

RX74M Group 1. Overview
Table 1.1 Outline of Specifications (2/10) Classification Module/Function Description
Memory Code MRAM Capacity: 512 Kbytes/1 Mbyte On-board programming: Five types A dual-bank structure allows programming during reading or exchanging the start-up areas Data MRAM Capacity: 48 Kbytes Programming: 100,000 times User extra MRAM Capacity: 128 Kbytes On-board programming: Five types Switchable to operate as MTJ-OTP Unique ID 128-bit unique ID for each device of this product family RAM Capacity: 1.5 Mbytes Error-correcting code (ECC), single-error correcting and double-error detecting code (SEC-DED) Local RAM Capacity: 128 Kbytes × 2 Up to 600 MHz, no-wait access Error-correcting code (ECC), single-error correcting and double-error detecting code (SEC-DED) Operating modes Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (SCI interface) Boot mode (USB interface) Boot mode (FINE interface) Boot mode (JTAG interface) Boot mode (SWD interface) Selection of operating mode by register setting Single-chip mode Endian selectable Clocks Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed/middle-speed/high-speed on-chip oscillator, and PLL frequency synthesizer (two circuits) The peripheral module clocks can be set to frequencies above that of the system clock. Main-clock oscillation stoppage detection Sub-clock oscillation stoppage detection Separate frequency-division and multiplication settings for the CPU clock (CPUCLK0), system clock (ICLK), MRAM code bus clock (MRICLK), MRAM peripheral clock (MRPCLK), peripheral module clocks (PCLKA, PCLKB, PCLKD, PCLKE), and external bus clock (BCLK) The CPU and local RAM run in synchronization with CPUCLK0: Up to 600 MHz The MRAM bus and code MRAM run in synchronization with MRICLK: Up to 300 MHz The data MRAM runs in synchronization with MRPCLK: Up to 150 MHz The RAM and other bus masters run in synchronization with the system clock (ICLK): Up to 300 MHz Peripheral modules of CRCA, DOCA, RSPIA, RSCI, ESWM, GPTW, HRPWM, POEG, DSMIF, ADC16H, CANFDG, CANFD, RSIP, RI3C, RIICHS, USBHS, and ESC run in synchronization with PCLKA, which operates at up to 150 MHz. Other peripheral modules run in synchronization with PCLKB: Up to 75 MHz The counter reference clock for the GPTW runs in synchronization with PCLKD: Up to 150 MHz The CANFDRAM runs in synchronization with PCLKE: Up to 300 MHz Devices connected to the external bus run in synchronization with BCLK: Up to 150 MHz The high-speed on-chip oscillator (HOCO) can be obtained through frequency- multiplication of the PLL1 or PLL2 reference clock External clock input frequency for the main clock oscillator: Up to 48 MHz External clock input frequency for the sub-clock oscillator: 32.768 kHz Clock output function R01DS0433EJ0110 Rev.1.10 Page 3 of 299 Jul 31, 2026 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 1.5.1 320-Pin LFBGA 1.5.2 224-Pin LFBGA 1.5.3 176-Pin LFBGA 1.5.4 176-Pin LFQFP 1.5.5 144-Pin LFQFP 1.5.6 100-Pin LFQFP 1.6 List of Pin and Pin Functions 1.6.1 320-Pin LFBGA 1.6.2 224-Pin LFBGA 1.6.3 176-Pin LFBGA 1.6.4 176-Pin LFQFP 1.6.5 144-Pin LFQFP 1.6.6 100-Pin LFQFP 2. Electrical Characteristics 2.1 Test Conditions 2.1.1 Maximum and Minimum Values (Max./Min.) 2.1.2 Typical Values (Typ.) 2.2 Absolute Maximum Ratings 2.3 Recommended Operating Conditions 2.4 DC Characteristics 2.4.1 Characteristics of the Input Voltage of the I/O Pins 2.4.2 Characteristics of the Output Voltage of the I/O Pins 2.4.3 Characteristics of the Other I/O Pins 2.4.4 Operating and Standby Currents 2.4.4.1 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = A, B, C, D, T, U, V, W) 2.4.4.2 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = E, F) 2.4.4.3 Currents in Deep Software Standby Mode 2.4.4.4 Other Operating Currents 2.4.4.5 Permissible Output Currents 2.4.5 Thermal Characteristics 2.4.5.1 Thermal Resistance Value 2.4.5.2 Supply Currents for the Peripheral Functions 2.4.5.3 Example of Calculation of Ta 2.4.6 VCC Rising and Falling Slopes and Ripple Frequency 2.5 AC Characteristics 2.5.1 Operating Frequency 2.5.2 Clock Timing 2.5.3 Reset Timing 2.5.4 Timing of Return from Low Power Consumption Modes 2.5.5 Control Signal Timing 2.5.6 Bus Timing 2.5.7 Timing of On-Chip Peripheral Modules 2.5.7.1 I/O Port 2.5.7.2 TMR 2.5.7.3 CMTW 2.5.7.4 POEG 2.5.7.5 GPTW 2.5.7.6 RSCI 2.5.7.7 RSPIA 2.5.7.8 XSPI 2.5.7.9 RIICHS 2.5.7.10 RI3C 2.5.7.11 SSIE 2.5.7.12 SD/MMC Host Interface 2.5.7.13 PDC 2.5.7.14 HRPWM 2.5.7.15 CANFD/CANFDG 2.5.7.16 ESC 2.5.7.17 ESWM 2.5.7.18 PDMIF 2.5.7.19 Δ-Σ Interface 2.5.7.20 PCIF 2.5.7.21 PIO 2.5.7.22 A/D Converter Trigger 2.5.7.23 CAC 2.6 USB Characteristics 2.6.1 USB Timing 2.6.2 USBHS Timing 2.7 A/D Conversion Characteristics 2.7.1 Analog Input Voltage Range 2.7.2 Common Characteristics of the 16-Bit A/D Converter 2.7.3 SAR Mode Characteristics 2.7.4 Common Characteristics of Oversampling Mode and Hybrid Mode 2.7.5 Oversampling Mode Characteristics 2.7.6 Hybrid Mode Characteristics 2.8 D/A Conversion Characteristics 2.9 Temperature Sensor Characteristics 2.10 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 2.11 Core Voltage Monitoring Reset Characteristics 2.12 Oscillation Stop Detection Timing 2.13 External VDD Timing Characteristics 2.14 Battery Backup Function Characteristics 2.15 MRAM Characteristics 2.15.1 Code MRAM Characteristics 2.15.2 Option-Setting Memory (MRAM Area) Characteristics 2.15.3 Option-Setting Memory (OTP Area with ECC) Characteristics 2.15.4 Option-Setting Memory (OTP Area without ECC) Characteristics 2.15.5 MACI Command Characteristics 2.15.6 W-HUK Zeroization Characteristics 2.15.7 MRAM Magnetic Field Resistance Characteristics 2.15.8 Data MRAM Characteristics 2.16 Boundary Scan 2.17 Usage Note 2.17.1 Connecting VCL Capacitor and Bypass Capacitors Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice