Datasheet RX74M (Renesas) - 6

RX74M Group 1. Overview
Table 1.1 Outline of Specifications (5/10) Classification Module/Function Description
I/O ports Software configurable Of the 64 port pins, up to 32 can be selected for simultaneous use. 32-bit programmable I/O Input or output can be enabled, and for outputs, the high or low level can be specified port (PIO) through register settings. Event link controller (ELC) Event signals such as interrupt request signals can be interlinked with the operation of functions such as timer counting, eliminating the need for intervention by the CPU to control the functions. 381 internal event signals can be freely combined for interlinked operation with connected functions. Event signals from peripheral modules can be used to change the states of output pins (of ports B, C, D, and E). Changes in the states of pins (of ports B, C, D, and E) being used as inputs can be interlinked with the operation of peripheral modules. Timers General PWM timer 32 bits × 16 channels (GPTW0 to GPTW15) (GPTW) Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable for all channels Clock sources independently selectable for each channel 2 input/output pins per channel 2 output compare/input capture registers per channel For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. In output compare operation, buffer switching can be at crests or troughs, enabling the generation of laterally asymmetrically PWM waveforms. Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) Generation of dead times in PWM operation Generation of highly accurate PWM waveforms with duty cycles close to the settings for values in the vicinity of duty 0% and 100%. In output compare operation, settings of the comparison registers are immediately reflected, and the generation of PWM waveforms with secured dead times is possible. Switching the direction of counting during operations in the triangle-wave PWM mode is possible. The counter can be synchronously started, stopped, cleared, or have its direction of counting switched in any channel. The counter can be started, stopped, cleared, or have its direction of counting switched, incremented, or decremented in response to up to eight ELC events. The counter can be started, stopped, cleared, or have its direction of counting switched, incremented, or decremented in response to detecting a state transition in one event input signal while another input signal is at a particular level. The counter can be started, stopped, cleared, or have its direction of counting switched, incremented, or decremented in response to up to four external triggers. Disabling of output on detection of a dead time error or a short-circuit among output pins is possible. Using a timer to generate a trigger signal to start A/D conversion is possible. The trigger signal can be output to the external pin is possible. Output of events, such as compare-matches from A to F, overflow, and underflow, to the ELC is possible. The noise filter of input capture is available. Cycle counting Measurement of the pulse width of the input signal Output of the result of a logical operation on the output signal from one channel and that from another channel is possible. Synchronous counter setting/counter clearing/input capture among channels The timer-linked synchronization signal output function enables synchronous operation between channels synchronized with the timer period, and synchronous operation with other IPs synchronized with the timer period. GTIOCnA/GTIOCnB pin input/output polarity inversion High resolution PWM Finely adjusting a PWM waveform generated by GPTW0 to GPTW3 with a minimum waveform generation resolution of approximately 49 ps is possible. circuit (HRPWMb) R01DS0433EJ0110 Rev.1.10 Page 6 of 299 Jul 31, 2026 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 1.5.1 320-Pin LFBGA 1.5.2 224-Pin LFBGA 1.5.3 176-Pin LFBGA 1.5.4 176-Pin LFQFP 1.5.5 144-Pin LFQFP 1.5.6 100-Pin LFQFP 1.6 List of Pin and Pin Functions 1.6.1 320-Pin LFBGA 1.6.2 224-Pin LFBGA 1.6.3 176-Pin LFBGA 1.6.4 176-Pin LFQFP 1.6.5 144-Pin LFQFP 1.6.6 100-Pin LFQFP 2. Electrical Characteristics 2.1 Test Conditions 2.1.1 Maximum and Minimum Values (Max./Min.) 2.1.2 Typical Values (Typ.) 2.2 Absolute Maximum Ratings 2.3 Recommended Operating Conditions 2.4 DC Characteristics 2.4.1 Characteristics of the Input Voltage of the I/O Pins 2.4.2 Characteristics of the Output Voltage of the I/O Pins 2.4.3 Characteristics of the Other I/O Pins 2.4.4 Operating and Standby Currents 2.4.4.1 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = A, B, C, D, T, U, V, W) 2.4.4.2 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = E, F) 2.4.4.3 Currents in Deep Software Standby Mode 2.4.4.4 Other Operating Currents 2.4.4.5 Permissible Output Currents 2.4.5 Thermal Characteristics 2.4.5.1 Thermal Resistance Value 2.4.5.2 Supply Currents for the Peripheral Functions 2.4.5.3 Example of Calculation of Ta 2.4.6 VCC Rising and Falling Slopes and Ripple Frequency 2.5 AC Characteristics 2.5.1 Operating Frequency 2.5.2 Clock Timing 2.5.3 Reset Timing 2.5.4 Timing of Return from Low Power Consumption Modes 2.5.5 Control Signal Timing 2.5.6 Bus Timing 2.5.7 Timing of On-Chip Peripheral Modules 2.5.7.1 I/O Port 2.5.7.2 TMR 2.5.7.3 CMTW 2.5.7.4 POEG 2.5.7.5 GPTW 2.5.7.6 RSCI 2.5.7.7 RSPIA 2.5.7.8 XSPI 2.5.7.9 RIICHS 2.5.7.10 RI3C 2.5.7.11 SSIE 2.5.7.12 SD/MMC Host Interface 2.5.7.13 PDC 2.5.7.14 HRPWM 2.5.7.15 CANFD/CANFDG 2.5.7.16 ESC 2.5.7.17 ESWM 2.5.7.18 PDMIF 2.5.7.19 Δ-Σ Interface 2.5.7.20 PCIF 2.5.7.21 PIO 2.5.7.22 A/D Converter Trigger 2.5.7.23 CAC 2.6 USB Characteristics 2.6.1 USB Timing 2.6.2 USBHS Timing 2.7 A/D Conversion Characteristics 2.7.1 Analog Input Voltage Range 2.7.2 Common Characteristics of the 16-Bit A/D Converter 2.7.3 SAR Mode Characteristics 2.7.4 Common Characteristics of Oversampling Mode and Hybrid Mode 2.7.5 Oversampling Mode Characteristics 2.7.6 Hybrid Mode Characteristics 2.8 D/A Conversion Characteristics 2.9 Temperature Sensor Characteristics 2.10 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 2.11 Core Voltage Monitoring Reset Characteristics 2.12 Oscillation Stop Detection Timing 2.13 External VDD Timing Characteristics 2.14 Battery Backup Function Characteristics 2.15 MRAM Characteristics 2.15.1 Code MRAM Characteristics 2.15.2 Option-Setting Memory (MRAM Area) Characteristics 2.15.3 Option-Setting Memory (OTP Area with ECC) Characteristics 2.15.4 Option-Setting Memory (OTP Area without ECC) Characteristics 2.15.5 MACI Command Characteristics 2.15.6 W-HUK Zeroization Characteristics 2.15.7 MRAM Magnetic Field Resistance Characteristics 2.15.8 Data MRAM Characteristics 2.16 Boundary Scan 2.17 Usage Note 2.17.1 Connecting VCL Capacitor and Bypass Capacitors Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice