Datasheet LT8418 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch in WLCSP-12 package |
| Seiten / Seite | 19 / 7 — Data Sheet. LT8418. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. BGN … |
| Dateiformat / Größe | PDF / 697 Kb |
| Dokumentensprache | Englisch |
Data Sheet. LT8418. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. BGN GND. VCC. INB. BGP. INT. TGN. TGP. BST. TOP VIEW. BALL SIDE DOWN
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 7 link to page 7
Data Sheet LT8418 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LT8418 1 2 3 4 A BGN GND VCC INB B BGP INT C SW VCC D TGN TGP BST SW TOP VIEW BALL SIDE DOWN (Not to Scale)
003
12-Ball WLCSP Package
Package Size: 1.67mm x 1.67mm, Ball Diameter: 0.26mm, Ball Pitch Size: 0.4mm
Figure 3. Pin Diagram Pin Descriptions Table 4. Pin Descriptions PIN NAME DESCRIPTION
Pull-down branch in bottom side split gate driver output. Adding a resistor from BGN to GaN A1 BGN FET’s gate can program the turn-off strength of the bottom side GaN FET. Ground. Connect this pin to the source of the bottom side GaN FET with low inductance and A2 GND resistance. Power supply for the internal control circuitry and gate drivers. Locally bypassing this pin to A3, C4
1
VCC ground with a minimum 4.7µF ceramic capacitor. PWM input to control bottom-side gate driver. INB is TTL input logic compatible, with a default A4 INB 200 kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used. Pull-up branch in bottom side split gate driver output. Adding a resistor from BGP to GaN FET’s B1 BGP gate can program the turn-on strength of the bottom side GaN FET. PWM input to control top-side gate driver. INT is TTL input logic compatible, with a default 200 B4 INT kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used. The minimum input pulse width for INT is 11ns. Switch Node. Connect SW to the source of the top synchronous GaN FET and the bottom C1, D4
1
SW terminal of the bootstrap capacitor with low inductance and resistance. Pull-down branch in top side split gate driver output. Adding a resistor from TGN to the GaN D1 TGN FET’s gate can program the turn-off strength of the top side GaN FET. Pull-up branch in top side split gate driver output. Adding a resistor from TGP to the GaN FET’s D2 TGP gate can program the turn-on strength of the top side GaN FET. Bootstrap Floating Driver Supply. The BST pin has an on-die bootstrap switch from the VCC, and an external bootstrap capacitor to the SW pin can be used to provide a stable and well- D3 BST balanced bootstrap voltage for the top side gate driver. Locally bypass this pin to SW with a minimum 100nF ceramic capacitor. 1 A3 and C4 are internally connected. C1 and D4 are internally connected.
analog.com
Rev 0 7 of 19 Document Outline Features Applications General Description Typical Application TABLE OF CONTENTS Revision History Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance Pin Configurations and Function Descriptions Pin Descriptions Block diagram Typical Performance Characteristics Theory of Operation 1.1. Chip Start-up, VCC UVLO/OVLO Protections 1.2. Input Interface INT, INB 1.3. Smart Bootstrap (BST) Switch and BST UVLO 1.4. Split Gate Driver Applications Information 1.1. Selecting the VCC and BST Capacitor 1.2. Selecting the Gate Resistance 1.3. Power Dissipation 1.4. PCB Bypass and Grounding Guideline 1.5. Soldering Guideline Outline Dimensions Typical Applications Ordering Guide Related Parts
Data Sheet LT8418 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LT8418 1 2 3 4 A BGN GND VCC INB B BGP INT C SW VCC D TGN TGP BST SW TOP VIEW BALL SIDE DOWN (Not to Scale)
003
12-Ball WLCSP Package
Package Size: 1.67mm x 1.67mm, Ball Diameter: 0.26mm, Ball Pitch Size: 0.4mm
Figure 3. Pin Diagram Pin Descriptions Table 4. Pin Descriptions PIN NAME DESCRIPTION
Pull-down branch in bottom side split gate driver output. Adding a resistor from BGN to GaN A1 BGN FET’s gate can program the turn-off strength of the bottom side GaN FET. Ground. Connect this pin to the source of the bottom side GaN FET with low inductance and A2 GND resistance. Power supply for the internal control circuitry and gate drivers. Locally bypassing this pin to A3, C4
1
VCC ground with a minimum 4.7µF ceramic capacitor. PWM input to control bottom-side gate driver. INB is TTL input logic compatible, with a default A4 INB 200 kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used. Pull-up branch in bottom side split gate driver output. Adding a resistor from BGP to GaN FET’s B1 BGP gate can program the turn-on strength of the bottom side GaN FET. PWM input to control top-side gate driver. INT is TTL input logic compatible, with a default 200 B4 INT kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used. The minimum input pulse width for INT is 11ns. Switch Node. Connect SW to the source of the top synchronous GaN FET and the bottom C1, D4
1
SW terminal of the bootstrap capacitor with low inductance and resistance. Pull-down branch in top side split gate driver output. Adding a resistor from TGN to the GaN D1 TGN FET’s gate can program the turn-off strength of the top side GaN FET. Pull-up branch in top side split gate driver output. Adding a resistor from TGP to the GaN FET’s D2 TGP gate can program the turn-on strength of the top side GaN FET. Bootstrap Floating Driver Supply. The BST pin has an on-die bootstrap switch from the VCC, and an external bootstrap capacitor to the SW pin can be used to provide a stable and well- D3 BST balanced bootstrap voltage for the top side gate driver. Locally bypass this pin to SW with a minimum 100nF ceramic capacitor. 1 A3 and C4 are internally connected. C1 and D4 are internally connected.
analog.com
Rev 0 7 of 19 Document Outline Features Applications General Description Typical Application TABLE OF CONTENTS Revision History Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance Pin Configurations and Function Descriptions Pin Descriptions Block diagram Typical Performance Characteristics Theory of Operation 1.1. Chip Start-up, VCC UVLO/OVLO Protections 1.2. Input Interface INT, INB 1.3. Smart Bootstrap (BST) Switch and BST UVLO 1.4. Split Gate Driver Applications Information 1.1. Selecting the VCC and BST Capacitor 1.2. Selecting the Gate Resistance 1.3. Power Dissipation 1.4. PCB Bypass and Grounding Guideline 1.5. Soldering Guideline Outline Dimensions Typical Applications Ordering Guide Related Parts