Datasheet EPC23110 (Efficient Power Conversion) - 10

eGaN® IC DATASHEET
EPC23110
Figure 12: Simplified Circuit Diagram of VIN , VDRV , VDD , and VBOOT Gate Driver Power Supplies
The EPC23110 IC integrates both HS and LS FET gate drivers with low V LSG impedance and high pulse current push-pull NFET output stage. Figure 13 IN V is the simplified circuit diagram of the gate driver output stage. DRV V Sync DDON
Figure 13: Simplified Circuit Diagram of Gate Driver
Q boot OFF drive Q 1 OFF2 drive
Output Stage
VDD SD/STB VDDON VBOOTON AGND Internal Driving Q V SA QSB BOOT Circuit M V PO DRV VDD Q Optional standby CB1 function disable A MSO MS1 The internal supplies can be disabled to save quiescent power by turning off the series switch, QSA in Figure 12, with 0 V applied to the STB/SD pin to engage chip standby mode. In this mode, minimum current is drawn from the external V The LS and HS gate drive voltage levels are derived from their respective DRV supply while VDD is open circuit. Whatever charge remains within the V internal low-side (VDD) and high-side (VBOOT) power supplies. To ensure DD bypass capacitor will be discharged by the chip internal circuits by I that the gate drive level (Q) is sufficiently close to VDD or VBOOT, an internal DRV_Q. driving circuit is used to turn-on MPO. Here MPO and MSO work similarly to In the chip standby circuit, series switch (QSA) between VDRV and VDD is the half-bridge power stage Q1 and Q2 output FETs except all the circuits turned off by an internal standby circuit which itself derives its power from are internal to the IC. CB1 is a representation of the internal capacitors VIN such that the chip draws a current IVIN_disable from VIN when standby used in the gate driving circuitry. The gate driver output (Q) is designed mode is engaged. The standby function requires a minimum input to reach 100% duty cycle, therefore the PWM input pulse width has no voltage of VIN,min for the IC to be enabled. Below VIN,min, the pass-transistor maximum boundaries, as long as VDD and/or VBOOT are above the power between VDRV and VDD will be off. To disable the standby function, and on reset threshold limit. At initial powerup, CB1 is not yet ful y charged, thus extend the minimum operating voltage to VIN(Boot Mode)min = 0 V , tie consequently, propagation delay (from HSIN, or LSIN, to SW) may increase, pins VDD and VDRV together. up to 250 ns. Only the first one, or two pulses may be affected. Figure 14 This is mandatory in boost converter applications, when DC input illustrates this behavior. voltage, applied to SW pin, is lower than 13.5 V (= VINmin + |VHS_DS_
Figure 14: Behavior before complete charging of internal gate
Clamp_0V|). Moreover, in boost mode, if the feed-through operation mode is required, it is recommended to use a Schottky diode in paral el to the
driver capacitors
high-side GaN FET to mitigate the losses during non-switching operation (both HS
V
IN and LSIN OFF, or there is no VDD). The series connected high
DD
voltage synchronous bootstrap FET, QSB in Figure 12, between VDD and V
VBOOT
BOOT for the high-side floating bootstrap supply is activated only after the LS FET (Q2) is turned on to avoid overcharging during deadtime.
HS
The use of GaN FET in the charging path eliminates reverse recovery
IN
and reduces power dissipation. Another advantage is the lower dropout
LSIN
voltage of approximately 100 mV from the synchronous FET versus typical Si bootstrap diode voltage of 0.6 V. With synchronous charging VBOOT is maintained closer to the VDD voltage, al owing the HS FET gate
SW
drive circuit to have similar gate drive current and delay performance as Normal operation CB1 of low side internal CB1 of high side internal the LS FET gate drive circuit. circuit is charging. Low side circuit is charging. High power FET may turn ON side power FET may turn with a longer propagation ON with a longer delay (max 250 ns) propagation delay (max 250 ns) or slower dv/dt EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 10