Datasheet OPA186 (Texas Instruments) - 10
| Hersteller | Texas Instruments |
| Beschreibung | Single, 24-V, low-power (90 μA) 5-μV-offset zero-drift op amp with rail-to-rail input and o |
| Seiten / Seite | 49 / 10 — OPA186, OP. A2186, OP. A4186. www.ti.com. 6.8 Typical Characteristics … |
| Dateiformat / Größe | PDF / 2.6 Mb |
| Dokumentensprache | Englisch |
OPA186, OP. A2186, OP. A4186. www.ti.com. 6.8 Typical Characteristics (continued). Figure 6-1. Offset Voltage Distribution
Modelllinie für dieses Datenblatt
Textversion des Dokuments
OPA186, OP A2186, OP A4186
SBOS968C – JUNE 2022 – REVISED JULY 2023
www.ti.com 6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted) 40 40 36 36 32 32 28 28 24 24 ers (%) fi 20 ers (%) fi 20 16 16 Ampli Ampli 12 12 8 8 4 4 0 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 Input Offset Voltage (µV) Offset Voltage Drift (µV/°C)
Figure 6-1. Offset Voltage Distribution Figure 6-2. Offset Voltage Drift (-40°C to 125C°C)
60 72 54 64 48 56 42 48 36 40 ers (%) ers (%) fi 30 fi 32 24 Ampli Ampli 24 18 16 12 6 8 0 0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -600 -400 -200 0 200 400 600 Input Bias Current (nA) Input Offset Current (pA)
Figure 6-3. Input Bias Current Distribution Figure 6-4. Input Offset Current Distribution
20 4 10 2 tage (µV) tage (µV) ol ol 0 0 Input Offset V -10 Input Offset V -2 -20 -4 -12.5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 12.5 4 6 8 10 12 14 16 18 20 22 24 Common-mode Voltage (V) Total Supply Voltage (V)
Figure 6-5. Offset Voltage vs Common-Mode Voltage Figure 6-6. Offset Voltage vs Supply Voltage
10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: OPA186 OPA2186 OPA4186 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA186 6.5 Thermal Information: OPA2186 6.6 Thermal Information: OPA4186 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Rail-to-Rail Inputs 7.3.2 Phase-Reversal Protection 7.3.3 Input Bias Current Clock Feedthrough 7.3.4 EMI Rejection 7.3.4.1 EMIRR +IN Test Configuration 7.3.5 Electrical Overstress 7.3.6 MUX-Friendly Inputs 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.1.1 Basic Noise Calculations 8.2 Typical Applications 8.2.1 High-Side Current Sensing 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 8.2.2 Bridge Amplifier 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.1.1.2 TINA-TI™ Simulation Software (Free Download) 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Mechanical, Packaging, and Orderable Information
SBOS968C – JUNE 2022 – REVISED JULY 2023
www.ti.com 6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted) 40 40 36 36 32 32 28 28 24 24 ers (%) fi 20 ers (%) fi 20 16 16 Ampli Ampli 12 12 8 8 4 4 0 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 Input Offset Voltage (µV) Offset Voltage Drift (µV/°C)
Figure 6-1. Offset Voltage Distribution Figure 6-2. Offset Voltage Drift (-40°C to 125C°C)
60 72 54 64 48 56 42 48 36 40 ers (%) ers (%) fi 30 fi 32 24 Ampli Ampli 24 18 16 12 6 8 0 0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -600 -400 -200 0 200 400 600 Input Bias Current (nA) Input Offset Current (pA)
Figure 6-3. Input Bias Current Distribution Figure 6-4. Input Offset Current Distribution
20 4 10 2 tage (µV) tage (µV) ol ol 0 0 Input Offset V -10 Input Offset V -2 -20 -4 -12.5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 12.5 4 6 8 10 12 14 16 18 20 22 24 Common-mode Voltage (V) Total Supply Voltage (V)
Figure 6-5. Offset Voltage vs Common-Mode Voltage Figure 6-6. Offset Voltage vs Supply Voltage
10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: OPA186 OPA2186 OPA4186 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA186 6.5 Thermal Information: OPA2186 6.6 Thermal Information: OPA4186 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Rail-to-Rail Inputs 7.3.2 Phase-Reversal Protection 7.3.3 Input Bias Current Clock Feedthrough 7.3.4 EMI Rejection 7.3.4.1 EMIRR +IN Test Configuration 7.3.5 Electrical Overstress 7.3.6 MUX-Friendly Inputs 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.1.1 Basic Noise Calculations 8.2 Typical Applications 8.2.1 High-Side Current Sensing 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 8.2.2 Bridge Amplifier 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.1.1.2 TINA-TI™ Simulation Software (Free Download) 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Mechanical, Packaging, and Orderable Information