Datasheet CAT5112 (ON Semiconductor) - 5

HerstellerON Semiconductor
Beschreibung32‐tap Digital Potentiometer (POT) with Buffered Wiper
Seiten / Seite11 / 5 — CAT5112. Table 4. DC ELECTRICAL CHARACTERISTICS. Symbol. Parameter. …
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DokumentenspracheEnglisch

CAT5112. Table 4. DC ELECTRICAL CHARACTERISTICS. Symbol. Parameter. Conditions. Min. Typ. Max. Units. POWER SUPPLY. LOGIC INPUTS

CAT5112 Table 4 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Units POWER SUPPLY LOGIC INPUTS

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CAT5112 Table 4. DC ELECTRICAL CHARACTERISTICS
(VCC = +2.5 V to +6 V unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units POWER SUPPLY
VCC Operating Voltage Range 2.5 – 6 V ICC1 Supply Current (Increment) VCC = 6 V, f = 1 MHz, IW = 0 – – 200 mA VCC = 6 V, f = 250 kHz, IW = 0 – – 100 mA ICC2 Supply Current (Write) Programming, VCC = 6 V – – 1000 mA VCC = 3 V – – 500 mA ISB1 (Note 4) Supply Current (Standby) CS = VCC − 0.3 V – 75 150 mA U/D, INC = VCC − 0.3 V or GND
LOGIC INPUTS
IIH Input Leakage Current VIN = VCC – – 10 mA IIL Input Leakage Current VIN = 0 V – – −10 mA VIH1 TTL High Level Input Voltage 4.5 V  VCC  5.5 V 2 – VCC V VIL1 TTL Low Level Input Voltage 0 – 0.8 V VIH2 CMOS High Level Input Voltage 2.5 V  VCC  6 V VCC x 0.7 – VCC + 0.3 V VIL2 CMOS Low Level Input Voltage −0.3 – VCC x 0.2 V
POTENTIOMETER CHARACTERISTICS
RPOT Potentiometer Resistance −10 Device 10 kW −50 Device 50 −00 Device 100 Pot. Resistance Tolerance 20 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 1 % INL Integral Linearity Error IW  2 mA 0.5 1 LSB DNL Differential Linearity Error IW  2 mA 0.25 0.5 LSB ROUT Buffer Output Resistance 0.05 VCC  VWB  0.95 VCC, 1 W VCC = 5 V IOUT Buffer Output Current 0.05 VCC  VWB  0.95 VCC, 3 mA VCC = 5 V TCRPOT TC of Pot Resistance 300 ppm/C TCRATIO Ratiometric TC 20 ppm/C CRH/CRL/CRW Potentiometer Capacitances 8/8/25 pF fc Frequency Response Passive Attenuator, 10 kW 1.7 MHz VWB(SWING) Output Voltage Range IOUT  100 mA, VCC = 5 V 0.01 VCC 0.99 VCC 3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V 5. IW = source or sink 6. These parameters are periodically sampled and are not 100% tested.
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