Datasheet CAT5112 (ON Semiconductor) - 4

HerstellerON Semiconductor
Beschreibung32‐tap Digital Potentiometer (POT) with Buffered Wiper
Seiten / Seite11 / 4 — CAT5112. Table 1. OPERATION MODES. INC. U/D. Operation. Figure 3. …
Dateiformat / GrößePDF / 230 Kb
DokumentenspracheEnglisch

CAT5112. Table 1. OPERATION MODES. INC. U/D. Operation. Figure 3. Potentiometer Equivalent Circuit

CAT5112 Table 1 OPERATION MODES INC U/D Operation Figure 3 Potentiometer Equivalent Circuit

Modelllinie für dieses Datenblatt

Textversion des Dokuments

link to page 4 link to page 4 link to page 4
CAT5112 Table 1. OPERATION MODES INC CS U/D Operation
High to Low Low High Wiper toward RH High to Low Low Low Wiper toward RL High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby RH CH RWI RWB CW CL RL
Figure 3. Potentiometer Equivalent Circuit Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units
Supply Voltage V VCC to GND −0.5 to +7 Inputs V CS to GND −0.5 to VCC +0.5 INC to GND −0.5 to VCC +0.5 V U/D to GND −0.5 to VCC +0.5 V RH to GND −0.5 to VCC +0.5 V RL to GND −0.5 to VCC +0.5 V RWB to GND −0.5 to VCC +0.5 V Operating Ambient Temperature C Commercial (‘C’ or Blank suffix) 0 to 70 Industrial (‘I’ suffix) −40 to +85 C Junction Temperature +150 C Storage Temperature −65 to +150 C Lead Soldering (10 s max) +300 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min Typ Max Units
VZAP (Note 1) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 V ILTH (Notes 1, 2) Latch-Up JEDEC Standard 17 100 mA TDR Data Retention MIL−STD−883, Test Method 1008 100 Years NEND Endurance MIL−STD−883, Test Method 1003 1,000,000 Stores 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V
http://onsemi.com 3