Datasheet ADGS1612 (Analog Devices) - 9

HerstellerAnalog Devices
BeschreibungSPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V, Mux Configurable, Quad SPST Switch
Seiten / Seite29 / 9 — Data Sheet. ADGS1612. 3.3 V SINGLE SUPPLY. Table 4. Parameter. 25°C. …
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Data Sheet. ADGS1612. 3.3 V SINGLE SUPPLY. Table 4. Parameter. 25°C. −40°C to +85°C. −40°C to +125°C. Unit. Test Conditions/Comments

Data Sheet ADGS1612 3.3 V SINGLE SUPPLY Table 4 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

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Data Sheet ADGS1612 3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = 0 V, VL = 2.7 V to 3.3 V, GND = 0 V, unless otherwise noted.
Table 4. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 3.2 3.4 3.6 Ω typ VS = 0 V to VDD, IS = −10 mA, VDD = 3.3 V, VSS = 0 V; see Figure 29 On Resistance Match Between Channels, 0.06 0.07 0.08 Ω typ VS = 0 V to VDD, IS = −10 mA ∆RON On Resistance Flatness, RFLAT(ON) 1.2 1.3 1.4 Ω typ VS = 0 V to VDD, IS = −10 mA LEAKAGE CURRENTS VDD = 3.3 V, VSS = 0 V Source Off Leakage, IS (Off ) ±0.1 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 32 ±0.3 ±1.0 ±6.0 nA max Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 32 ±0.3 ±1.0 ±6.0 nA max Channel On Leakage, ID (On), IS (On) ±0.2 VS = VD = 0.6 V/3 V; see Figure 28 ±0.4 ±1.5 ±10.0 V max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA 0.2 V max ISINK = 1 mA Output Current, Low (IOL) or High (IOH) 0.001 μA typ VOUT = VGND or VL ±0.1 μA max Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 1.35 V min Low, VINL 0.8 V max Input Current, Low (IINL) or High (IINH) 0.001 μA typ VIN = VGND or VL ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS On Time, tON 545 ns typ RL = 300 Ω, CL = 35 pF 720 730 735 ns max VS = 1.5 V; see Figure 36 Off Time, tOFF 470 ns typ RL = 300 Ω, CL = 35 pF 630 695 760 ns max VS = 1.5 V; see Figure 36 Break-Before-Make Time Delay, tD 155 ns typ RL = 300 Ω, CL = 35 pF 50 ns min VS1 = VS2 = 1.5 V, see Figure 35 Charge Injection, QINJ 50 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 37 Off Isolation −65 dB typ CL = 5 pF, f = 100 kHz; see Figure 31 Channel to Channel Crosstalk −93 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Total Harmonic Distortion Plus Noise, 0.18 % typ RL = 110 Ω, f = 20 Hz to 20 kHz, THD + N VS = 2 V p-p; see Figure 33 −3 dB Bandwidth 50 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 34 Insertion Loss −0.27 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Off Switch Source Capacitance, CS (Off ) 76 pF typ VS = 1.5 V, f = 1 MHz Off Switch Drain Capacitance, CD (Off ) 76 pF typ VS = 1.5 V, f = 1 MHz On Switch Capacitance, CD (On), CS (On) 160 pF typ VS = 1.5 V, f = 1 MHz Rev. 0 | Page 9 of 29 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ±5 V Dual Supply 12 V Single Supply 5 V Single Supply 3.3 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information Break-Before-Make Switching Digital Input Buffers Power Supply Rails Register Summary Register Details Switch Data Register Address: 0x01, Reset: 0x00, Name: SW_DATA Error Configuration Register Address: 0x02, Reset: 0x06, Name: ERR_CONFIG Error Flags Register Address: 0x03, Reset: 0x00, Name: ERR_FLAGS Burst Enable Register Address: 0x05, Reset: 0x00, Name: BURST_EN Software Reset Register Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB Outline Dimensions Ordering Guide