Datasheet ADGS1612 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V, Mux Configurable, Quad SPST Switch |
| Seiten / Seite | 29 / 2 — ADGS1612. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. … |
| Dateiformat / Größe | PDF / 382 Kb |
| Dokumentensprache | Englisch |
ADGS1612. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 1/2018—Revision 0: Initial Version
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ADGS1612 Data Sheet TABLE OF CONTENTS
Features .. 1 Address Mode ... 22 Applications ... 1 Error Detection Features ... 22 Functional Block Diagram .. 1 Clearing the Error Flags Register ... 23 General Description ... 1 Burst Mode .. 23 Product Highlights ... 1 Software Reset ... 23 Revision History ... 2 Daisy-Chain Mode ... 23 Specifications ... 3 Power-On Reset .. 24 ±5 V Dual Supply ... 3 Applications Information .. 25 12 V Single Supply .. 5 Break-Before-Make Switching .. 25 5 V Single Supply .. 7 Digital Input Buffers .. 25 3.3 V Single Supply ... 9 Power Supply Rails ... 25 Continuous Current per Channel, Sx or Dx ... 11 Register Summary .. 26 Timing Characteristics .. 11 Register Details ... 27 Absolute Maximum Ratings .. 13 Switch Data Register .. 27 Thermal Resistance .. 13 Error Configuration Register .. 27 ESD Caution .. 13 Error Flags Register .. 28 Pin Configuration and Function Descriptions ... 14 Burst Enable Register ... 28 Typical Performance Characteristics ... 15 Software Reset Register ... 28 Test Circuits ... 19 Outline Dimensions ... 29 Terminology .. 21 Ordering Guide .. 29 Theory of Operation .. 22
REVISION HISTORY 1/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 29 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ±5 V Dual Supply 12 V Single Supply 5 V Single Supply 3.3 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information Break-Before-Make Switching Digital Input Buffers Power Supply Rails Register Summary Register Details Switch Data Register Address: 0x01, Reset: 0x00, Name: SW_DATA Error Configuration Register Address: 0x02, Reset: 0x06, Name: ERR_CONFIG Error Flags Register Address: 0x03, Reset: 0x00, Name: ERR_FLAGS Burst Enable Register Address: 0x05, Reset: 0x00, Name: BURST_EN Software Reset Register Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB Outline Dimensions Ordering Guide
ADGS1612 Data Sheet TABLE OF CONTENTS
Features .. 1 Address Mode ... 22 Applications ... 1 Error Detection Features ... 22 Functional Block Diagram .. 1 Clearing the Error Flags Register ... 23 General Description ... 1 Burst Mode .. 23 Product Highlights ... 1 Software Reset ... 23 Revision History ... 2 Daisy-Chain Mode ... 23 Specifications ... 3 Power-On Reset .. 24 ±5 V Dual Supply ... 3 Applications Information .. 25 12 V Single Supply .. 5 Break-Before-Make Switching .. 25 5 V Single Supply .. 7 Digital Input Buffers .. 25 3.3 V Single Supply ... 9 Power Supply Rails ... 25 Continuous Current per Channel, Sx or Dx ... 11 Register Summary .. 26 Timing Characteristics .. 11 Register Details ... 27 Absolute Maximum Ratings .. 13 Switch Data Register .. 27 Thermal Resistance .. 13 Error Configuration Register .. 27 ESD Caution .. 13 Error Flags Register .. 28 Pin Configuration and Function Descriptions ... 14 Burst Enable Register ... 28 Typical Performance Characteristics ... 15 Software Reset Register ... 28 Test Circuits ... 19 Outline Dimensions ... 29 Terminology .. 21 Ordering Guide .. 29 Theory of Operation .. 22
REVISION HISTORY 1/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 29 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ±5 V Dual Supply 12 V Single Supply 5 V Single Supply 3.3 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information Break-Before-Make Switching Digital Input Buffers Power Supply Rails Register Summary Register Details Switch Data Register Address: 0x01, Reset: 0x00, Name: SW_DATA Error Configuration Register Address: 0x02, Reset: 0x06, Name: ERR_CONFIG Error Flags Register Address: 0x03, Reset: 0x00, Name: ERR_FLAGS Burst Enable Register Address: 0x05, Reset: 0x00, Name: BURST_EN Software Reset Register Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB Outline Dimensions Ordering Guide