Datasheet AD5522 (Analog Devices)

HerstellerAnalog Devices
BeschreibungQuad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs
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RevisionF
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Quad Parametric Measurement Unit with. Integrated 16-Bit Level Setting DACs. Data Sheet. AD5522. FEATURES. APPLICATIONS

Datasheet AD5522 Analog Devices, Revision: F

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Quad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs Data Sheet AD5522 FEATURES APPLICATIONS Quad parametric measurement unit (PMU) Automated test equipment (ATE) FV, FI, FN (high-Z), MV, MI functions Per-pin parametric measurement unit 4 programmable current ranges (internal RSENSE) Continuity and leakage testing ±5 μA, ±20 μA, ±200 μA, and ±2 mA Device power supply 1 programmable current range up to ±80 mA (external RSENSE) Instrumentation 22.5 V FV range with asymmetrical operation Source measure unit (SMU) Integrated 16-bit DACs provide programmable levels Precision measurement Gain and offset correction on chip Low capacitance outputs suited to relayless systems On-chip comparators per channel FI voltage clamps and FV current clamps Guard drive amplifier System PMU connections Programmable temperature shutdown SPI- and LVDS-compatible interfaces Compact 80-lead TQFP with exposed pad (top or bottom) FUNCTIONAL BLOCK DIAGRAM AGND AVSS AVDD DVCC DGND CCOMP[0:3] SYS_FORCE SYS_SENSE EN EXTFOH[0:3] VREF 16-BIT 16 16 ×4 X1 REG CLH DAC CLH CFF[0:3] 16 X2 REG SW3 M REG REFGND ×2 16 C REG ×2 OFFSET DAC INTERNAL RANGE SELECT 16 FIN 60Ω 1kΩ 16 (±5µA, ±20µA, ±200µA, ±2mA) ×6 SW1 16 16-BIT X1 REG + 16 FIN DAC + M REG AGND FOH[0:3] X2 REG FORCE C REG MEASVH AMPLIFIER ×6 (Hi-Z) SW5 RSENSE SW2 SW6 4kΩ SW4 16 16 16-BIT X1 REG CLL DAC CLL EXTMEASIH[0:3] 16 X2 REG M REG VMID TO ×2 + 16 CENTER EXTERNA L C REG SW8 SW10 ×2 I RANGE RSENSE 2kΩ SW7 (CURRENTS + ×5 or ×10 EXTMEASIL[0:3] UP TO ±80mA) MEASOUT + MEASOUT[0:3] MUX AND GAIN SW9 ×1/×0.2 SW12 TEMP 4kΩ MEASURE SENSOR CURRENT AGND 16 SW11 IN-AMP MEASVH[0:3] ×6 16 ×6 + 16 X1 REG 16 16-BIT GUARD[0:3] M REG CPH DAC X2 REG AGND SW13 DUT C REG + SW16 GUARDIN[0:3]/ ×1 GUARD AMP DUTGND[0:3] 16 CPH DUTGND 16 ×6 ×6 + SW14 CPL 16-BIT DUTGND 16 X1 REG 16 CPL DAC M REG X2 REG + + MEASURE C REG VOLTAGE SW15 IN-AMP COMPARATOR 10kΩ AGND 16-BIT TO ALL DAC 16 OFFSET TO OUTPUT TEMP DAC MEASOUT AMPLIFIERS SENSOR TMPALM MUX 16 SERIAL CLAMP AND POWER-ON INTERFACE GUARD CGALM RESET ALARM
001
RESET SDO SCLK SDI SYNC BUSY LOAD SPI/ CPOL0/ CPOH0/ CPOL1/ CPOH1/ CPOL2/ CPOH2/ CPOL3/ CPOH3/ LVDS SCLK SDI SYNC SDO CPO0 CPO1 CPO2 CPO3
06197- Figure 1.
Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Force Amplifier Comparators Clamps Current Range Selection High Current Ranges Measure Current Gains VMID Voltage Choosing Power Supply Rails Measure Output (MEASOUTx Pins) Device Under Test Ground (DUTGND) Guard Amplifier Compensation Capacitors System Force and Sense Switches Temperature Sensor DAC Levels Offset DAC Gain and Offset Registers Cached X2 Registers Gain and Offset Registers for the FIN DAC Gain and Offset Registers for the Comparator DACs Gain and Offset Registers for the Clamp DACs Reference Voltage (VREF) Reference Selection Reference Selection Example Calibration Reducing Zero-Scale Error Reducing Gain Error Calibration Example Additional Calibration System Level Calibration Circuit Operation Force Voltage (FV) Mode Force Current (FI) Mode Serial Interface SPI Interface LVDS Interface Serial Interface Write Mode RESETB Function BUSYB and LOADB Functions Register Update Rates Register Selection Readback Control, RD/WRB PMU Address Bits: PMU3, PMU2, PMU1, PMU0 NOP (No Operation) Reserved Commands Write System Control Register Write PMU Register Write DAC Register DAC Addressing Read Registers Readback of System Control Register Readback of PMU Register Readback of Comparator Status Register Readback of Alarm Status Register Readback of DAC Register Applications Information Power-On Default Setting Up the Device on Power-On Changing Modes Required External Components Power Supply Decoupling Power Supply Sequencing Typical Application for the AD5522 Outline Dimensions Ordering Guide