Datasheet ADPA7005CHIP (Analog Devices) - 5

Data Sheet ADPA7005CHIP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGG1 VDD5 V V DD3 DD1 VREF 2 3 4 5 6 1 RFIN 7 RFOUT ADPA7005 TOP VIEW (Not to Scale) VDET 8 12 11 10 9
002
V V V V GG2 DD6 DD4 DD2
17319- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 RFIN RF Signal Input. This pad is ac-coupled and matched to 50 Ω. 2, 12 VGG1, VGG2 Amplifier Gate Control. External bypass capacitors of 4.7 μF, 0.01 μF, and 100 pF are required. ESD protection diodes are included and turn on below −1.5 V. 3, 4, 5, 9, 10, 11 VDD5, VDD3, VDD1, VDD2, VDD4, VDD6 Drain Bias for the amplifier. External bypass capacitors of 4.7 μF, 0.01 μF, and 100 pF are required. 6 VREF Reference Diode. Use this pin in combination with VDET. The voltage provides temperature compensation to the VDET RF output power measurements. 7 RFOUT RF Signal Output. This pad is ac-coupled and matched to 50 Ω. 8 VDET Detector Diode Used for Measuring the RF Output Power. Detection via this pin requires the application of a dc bias voltage through an external series resistor. Used in combination with VREF, the difference voltage, VREF − VDET, is a temperature compensated dc voltage proportional to the RF output power. Die Bottom GND Ground. The pads and die bottom must be connected to RF and dc ground. Rev. 0 | Page 5 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC CONSTANT IDD OPERATION THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding BIASING ADPA7005CHIP WITH THE HMC980LP4E APPLICATION CIRCUIT SETUP LIMITING VGATE FOR ADPA7005CHIP VGGx ABSOLUTE MAXIMUM RATING REQUIREMENT HMC980LP4E BIAS SEQUENCE Power-Up Sequence Power-Down Sequence CONSTANT DRAIN CURRENT BIASING vs. CONSTANT GATE VOLTAGE BIASING TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE