Datasheet MAX4684, MAX4685 (Maxim) - 8

MAX4684/MAX4685 0.5Ω/0.8Ω Low-Voltage, Dual SPDT Analog Switches in UCSP
Test Circuits/Timing Diagrams MAX4684
V+ tr < 5ns
MAX4685
VIH t LOGIC f < 5ns 50% V+ INPUT V NO_ COM_ IL VIN_ V OR NC OUT RL CL t 50Ω OFF 35pF IN_ VOUT 0.9 x V0UT 0.9 x VOUT LOGIC GND SWITCH 0 INPUT OUTPUT tON CL INCLUDES FIXTURE AND STRAY CAPACITANCE. LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES V THAT HAVE THE OPPOSITE LOGIC SENSE. OUT = VN_ ( RL R ) L + RON Figure 2. Switching Time V+
MAX4684
VIH
MAX4685
LOGIC 50% V+ INPUT VIL NC_ VN_ COM_ VOUT NO_ RL C 50Ω L IN_ 35pF LOGIC GND INPUT V 0.9 x V OUT OUT tD CL INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 3. Break-Before-Make Interval V+ ∆VOUT
MAX4684 MAX4685
V+ VOUT RGEN NC_ COM_ VOUT OR NO_ IN CL OFF OFF VGEN ON GND IN_ ON OFF OFF IN VIL TO VIH Q = (∆VOUT)(CL) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 4. Charge Injection www.maximintegrated.com Maxim Integrated │

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