Datasheet MIN1072M MinE-CAP (Power Integrations) - 8

MinE-CAP Layout Considerations
The fol owing layout considerations are specifical y for the MinE-CAP 5. Tie the GROUND pins to a copper plane for heat dissipation. If a components. For placement and layout of InnoSwitch3-specific and large copper plane is not possible, thermal vias can also be used power components, check the InnoSwitch3-Pro data sheet. for boards with 2 or more copper layers. The MinE-CAP IC and InnoSwitch3-Pro IC can share the same GND plane. 1. The MinE-CAP sense pins (VBOT and VTOP) and InnoSwitch3 IC’s V pin use current in the mA range to measure line and capacitor 6. Place both input bulk capacitors in such a way to minimize the voltages. Avoid routing lines with high dV/dt or dI/dt signals near primary switching loop. Prioritize placing the high-voltage these pins. This rule must also be observed for the LINE pin. capacitor closer to the transformer and InnoSwitch3-Pro IC since this capacitor is always part of the high-frequency switching loop. 2. Signal lines going to the pins stated above must also be routed away from high dV/dt or dI/dt nodes or tracks. 7. Clean the board properly to prevent flux residues from interfering with the signals. 3. All resistors associated with the MinE-CAP IC, except for the bleed resistor in paral el with C must be placed near the Figures 9 shows the MinE-CAP layout used for the design in Figure 8 LV MinE-CAP IC. fol owing the recommendation stated above. In this design, the layout did not permit the RTOP to be placed right next to the VTOP 4. Place the MinE-CAP IC as close as possible to the InnoSwitch3-Pro pin. However, the VTOP pin trace is shielded by a ground plane IC to minimize the trace from the LINE pin to the V pin of the beside and beneath the trace. Additional y, there are no high di/dt or Innowitch IC. Placing the MinE-CAP IC next to the InnoSwitch3 dv/dt signals near the track, pin or resistor. IC also al ows the use of a single bypass capacitor for both ICs.
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Rev. D 11/20 www.power.com