Datasheet AD74413R (Analog Devices) - 6

AD74413R Data Sheet CURRENT OUTPUT
AVDD = 14 V to 28.8 V, AGND = DGND = 0 V, REFIN = 2.5 V (ideal), DVCC = 2.7 V to 5.5 V, IOVDD= 1.7 V to 5.5 V, and all specifications at TA = −40°C to +105°C, unless otherwise noted. RLOAD = 250 Ω, CLOAD = 10 nF per recommended configuration, and the sense resistor (RSENSE) = 100 Ω (ideal).
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT OUTPUT

Resolution 13 Bits Output Range 0 25 mA ACCURACY TUE1 −0.28 +0.28 %FSR TUE at 25°C −0.2 +0.2 %FSR INL −3 +3 LSB From zero-scale to full-scale DNL −1 +1 LSB Guaranteed monotonic Offset Error −15 2.0 +15 μA Offset Error at 25°C1 −11 +11 μA Gain Error1 −0.3 +0.3 %FSR Gain Error at 25°C1 −0.25 +0.25 %FSR OUTPUT CHARACTERISTICS Headroom 4.6 V Minimum voltage difference required between AVDD and the I/OP_x screw terminal to source 25 mA Open Circuit Voltage AVDD V Output Impedance 1.5 4 MΩ DC PSRR2 200 nA/V PSRR measured with a change in AVDD DYNAMIC PERFORMANCE2 Output Current Settling Time 230 μs 25 mA step up or down, time to settle within a window of ±100 μA of final current Output Current Settling Time (with 55 ms With HART slew enabled, 25 mA step up or step down, HART® Slew Enabled) time to settle within a window of ±100 μA of final current Noise Measured at the I/OP_x screw terminal with 250 Ω load, 12.5 mA output Output Noise 0.15 LSB p-p 0.1 Hz to 10 Hz bandwidth Output Noise Spectral Density 2 nA/√Hz Measured at 1 kHz, 12.5 mA output AC PSRR 80 dB Voltage on the supply at 1 kHz to the voltage across the 250 Ω. 1 RSENSE accuracy directly impacts the TUE and gain error. 2 Guaranteed by design and characterization. Rev. 0 | Page 6 of 70 Document Outline Features Applications General Description Companion Products Product Highlights Revision History Functional Block Diagram Specifications Voltage Output Current Output Voltage Input Current Input Externally Powered and Current Input Externally Powered with HART Current Input Loop Powered Resistance Measurement Digital Input Logic Digital Input Loop Powered ADC Specifications General Specifications Timing Characteristics SPI Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Digital Input Resistance Measurement Reference ADC Supplies Theory of Operation Robust Architecture Serial Interface DAC Architecture ADC Overview Reference Reference Noise Charge Pump Power-On State of the AD74413R Device Functions High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpreting ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data HART Compatibility Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Thermocouple Measurement Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Externally Powered with HART Compatibility Mode Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered with HART Compatibility Mode Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Threshold Setting Digital Input Current Sink Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter Digital Input Counter Digital Input, Loop Powered Mode Interpreting ADC Data Getting Started Using Channel Functions Switching Channel Functions ADC Functionality ADC Conversion Rates ADC_RDYb Functionality ADC Output Data Format ADC Noise Diagnostics DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control HART Compliant Slew Driving Inductive Loads Reset Function Thermal Alert and Thermal Reset Faults and Alerts Channel Faults Power Supply Monitors GPO_x Pins SPI Interface and Diagnostics SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback Board Design and Layout Considerations Applications Information Register Map NOP Register Function Setup Register per Channel ADC Configuration Register per Channel Digital Input Configuration Register per Channel GPO Parallel Data Register GPO Configuration Register per Channel Output Configuration Register per Channel DAC Code Register per Channel DAC Clear Code Register per Channel DAC Active Code Register per Channel Digital Input Threshold Register ADC Conversion Control Register Diagnostics Select Register Digital Output Level Register ADC Conversion Results Register per Channel Diagnostic Results Registers per Diagnostic Channel Alert Status Register Live Status Register Alert Mask Register Debounced DIN Count Register per Channel Readback Select Register Thermal Reset Enable Register Command Register Scratch or Spare Register Silicon Revision Register Outline Dimensions Ordering Guide