Datasheet AD2420(W), AD2426(W), AD2427(W), AD2428(W), AD2429(W) (Analog Devices) - 4

HerstellerAnalog Devices
BeschreibungAutomotive Audio Bus A2B Transceiver
Seiten / Seite38 / 4 — AD2420(W). /AD2426(W). /AD2427(W). /AD2428(W). AD2429(W). A2B BUS …
RevisionB
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AD2420(W). /AD2426(W). /AD2427(W). /AD2428(W). AD2429(W). A2B BUS DETAILS. MASTER. I2S/TDM. A2B. HOST. TRANSCEIVER. DSP. I2C. A B. SLAVE A2B

AD2420(W) /AD2426(W) /AD2427(W) /AD2428(W) AD2429(W) A2B BUS DETAILS MASTER I2S/TDM A2B HOST TRANSCEIVER DSP I2C A B SLAVE A2B

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AD2420(W) /AD2426(W) /AD2427(W) /AD2428(W) / AD2429(W) A2B BUS DETAILS
control frame. Every slave can use or consume some of the downstream data and add data for downstream nodes. The last Figure 2 shows a single-master, multiple-slave A2B communica- slave node transceiver responds after the response time with a tions system with the master transceiver controlled by the host. synchronization response frame (SRF). Upstream synchronous The host generates a periodic synchronization signal on the data is added by each node directly after the response frame. I2S/TDM interface at a fixed frequency (typically 48 kHz) to Each node can also use or consume upstream data. which all A2B nodes synchronize. The embedded control and response frames allow the host to Communications along the A2B bus occur in periodic super- individually address each slave transceiver in the system. The frames. The superframe frequency is the same as the host also enables access to remote peripheral devices that are synchronization signal frequency, and data is transferred at a bit connected to the slave transceivers via the I2C or SPI ports for rate that is 1024 times faster (typically 49.152 MHz). Each I2C to I2C communication over distance between multiple superframe is divided into periods of downstream transmission, nodes. upstream transmission, and no transmission (where the bus is not driven). Data is exchanged over the A2B bus in up to 32 All nodes in an A2B system are sampled synchronously in the equal width slots for both upstream and downstream same A2B superframe. Synchronous I2S/TDM downstream data transmissions. from the master arrives at all slaves in the same A2B superframe, and the upstream audio data of every node arrives synchro- The A2B bus also communicates the following control and nously in the same I2S/TDM frame at the master. The remaining status information between nodes: audio phase differences between slaves can be compensated for • I2C to I2C communication by register-programmable fine adjustment of the SYNC pin sig- • General-purpose input/output (GPIO) nal delay. • Interrupts There is a sample delay incurred for data moving between the A2B bus and the I2S/TDM interfaces because data is received and transmitted over the I2S/TDM every sample period (typi- cally 48 kHz). This timing relationship between samples over
MASTER I2S/TDM
the A2B bus is shown in Figure 4.
A2B
Note in Figure 4, both downstream and upstream samples are
HOST TRANSCEIVER DSP
named for the frame where they enter the A2B system as follows:
2 I2C A B
• Data transmitted by the master node transceiver in Super- frame M creates Downstream Data M.
SLAVE A2B I2S/TDM TRANSCEIVER
• Data transmitted by the slave node transceivers in Super- frame N creates Upstream Data N.
2 A B I2C
• Data received over the I2S/TDM interface by the A2B trans- ceiver is transmitted over the A2B bus in the next
SLAVE A2B I2S/TDM
superframe.
TRANSCEIVER
• Data on the A2B bus is transmitted over the I2S/TDM inter-
I2C
face of an A2B transceiver in the next superframe.
2 A B
• Data transmitted across the A2B bus (master to slave or slave to master) has two frames of latency plus any internal delay that has accumulated in the transceivers as well as
SLAVE A2B I2S/TDM
delays due to wire length. Therefore, overall latency is
TRANSCEIVER
slightly over two samples (<50 μs at 48 kHz sample periods) from the I2S/TDM interface in one A2B transceiver to the
I2C
I2S/TDM interface of another A2B transceiver. To support and extend the A2B bus functions and performance, Figure 2. Communication System Block Diagram the transceivers have additional features, as described in the fol- lowing sections. In Figure 3, a superframe is shown with an initial period of downstream transmission and a later period of upstream transmission. All signals on the A2B bus are line coded, and the master node forwards the synchronization signal downstream from the mas- ter transceiver to the last slave node transceiver in the form of a synchronization preamble. This preamble is followed by control data to build a synchronization control frame (SCF). Down- stream, TDM synchronous data is added directly after the Rev. B | Page 4 of 38 | January 2020 Document Outline Automotive Audio Bus A2B Transceiver A2B Bus Features A2B Transceiver Features Applications Table of Contents Revision History General Description A2B Bus Details I2C Interface I2S/TDM Interface I2S Reduced Rate Pulse Density Modulation (PDM) Interface GPIO Over Distance Mailboxes Data Slot Exchange Between Slaves Clock Sustain State Programmable Settings to Optimize EMC Performance Programmable LVDS Transmit Levels Spread-Spectrum Clocking Unique ID Support for Crossover or Straight Through Cabling Data Only and Power Only Bus Operation Specifications Operating Conditions Electrical Characteristics Power Supply Rejection Ratio (PSRR) Timing Specifications Power-Up Sequencing Restrictions A2B Bus System Specification RMS Time Interval Error (TIE) Jitter PDM Typical Performance Characteristics Absolute Maximum Ratings Thermal Characteristics ESD Caution Test Circuits and Switching Characteristics Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Pin Configuration and Function Descriptions Power Analysis Current Flow Constant Current PLL Supply Current VIN Quiescent Current IOVDD Current Peripheral Supply Current Digital Logic Supply Current A2B Bus TX/RX Current LVDS Transmitter and Receiver Supply Currents Downstream/Upstream Activity Level LVDS Transmitter and Receiver Idle Current VREG1 and VREG2 Output Currents Current at VIN (IVIN) Power Dissipation Resistance Between Nodes Voltage Regulator Current in Master Node or Local Powered Slave Node Power Dissipation of A2B Bus Power Analysis of Bus Powered System Supply Voltage Reducing Power Consumption Power-Down Mode Standby Mode Control Mode Thermal Power Designer Reference VSENSE and Considerations for Diodes Optional Add On Circuits Layout Guidelines Outline Dimensions Automotive Products Ordering Guide