P9415 Preliminary Datasheet Theory of Operation / Application/ Descriptive Content Figure 3. Internal Block Diagram BST1 BST2 nEN LDO5P0 VRECT nEN&UVLO LDO5V AC1 BIAS M_LDO AC2 VOUT T/RX control 500MHz OSC Is_out G P Is_ VOUT IO tx LDO1P8 LDO1P8 VRECT ECLAMP Gate ECLAMP_DRV AC1 AC2 Driver DAC Freq Det 12b ADC +Comp CMA1 CMA2 CMB1 CMB2 ARM M0 Controller (w/ 24KB MTP, 8 KB RAM) V Is V R _ R E o E C u F T t AFE(TX) OSC - OVP + PCLAMP 60MHz l Load Digital IO (GPIO) DEMOD OD0(SCL)/OD1(SDA)/GP0-GP6/OD2-OD4