Datasheet LTM4651 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | EN55022B Compliant 58V, 24W Inverting-Output DC/DC μModule Regulator |
| Seiten / Seite | 36 / 9 — PIN FUNCTIONS. COMPa (E2):. PGOOD (D1):. PGDFB (D2):. COMPb (E1):. VINREG … |
| Revision | A |
| Dateiformat / Größe | PDF / 2.2 Mb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. COMPa (E2):. PGOOD (D1):. PGDFB (D2):. COMPb (E1):. VINREG (D3):. SET (E3):. CLKIN (B1):. TEMP+ (J1, J6):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTM4651
PIN FUNCTIONS
In addition, the output of the LTM4651 can track a voltage
COMPa (E2):
Current Control Threshold and Error Ampli- applied between the ISETa pin and the SV – OUT pins. See fier Compensation Node. The trip threshold of LTM4651’s the Applications Information section. current comparator increases with a respective rise in
PGOOD (D1):
Power Good Indicator, Open-Drain Output COMPa voltage. A small filter capacitor (10pF) internal Pin. PGOOD is high impedance when PGDFB – SV – to the LTM4651 on this pin introduces a high-frequency OUT is within approximately ±7.5% of 0.6V. PGOOD is pulled to roll-off of the error-amplifier response, yielding good noise GND when PGDFB – SV – rejection in the control-loop. COMPa is usually electrically OUT is outside this range. connected to COMPb in one’s application, thus applying
PGDFB (D2):
Power Good Feedback Programming Pin. default loop compensation. Loop compensation (a series Connect PGDFB to GNDSNS through a resistor, RPGDFB. resistor-capacitor) can be applied externally to COMPa if R – PGDFB configures the voltage threshold of VOUT for desired or needed, instead. See COMPb. which PGOOD toggles its state. If the PGOOD feature is used, set R
COMPb (E1):
Internal Loop Compensation Network. PGDFB to: For a majority of applications, the internal, default loop ⎛ ⎞ ⎜ | V – | compensation of the LTM4651 is suitable to apply “as is” R OUT ⎟ PGDFB = ⎜ – 1 • 4.99k ⎜ 0.6V ⎟⎟ and yields very satisfactory results: apply the default loop ⎝ ⎠ compensation to the control loop by simply connecting COMPa to COMPb. When more specialized applications otherwise, leave PGDFB open circuit. require a personal touch to the optimization of control loop A small filter capacitor (220pF) internal to the LTM4651 response, this can be accomplished by connecting a series – on this pin provides high frequency noise immunity for resistor-capacitor network from COMPa to SVOUT —and the PGOOD output indicator. leaving COMPb open circuit.
f VINREG (D3):
Input Voltage Regulation Programming Pin.
SET (E3):
Oscillator Frequency Programming Pin. The default switching frequency of the LTM4651 is 400kHz. Optionally connect this pin to the midpoint node formed – Often, it is necessary to increase the programmed fre- by a resistor-divider between VD and SVOUT . When the quency by connecting a resistor between f – voltage on VINREG falls below approximately 2V with SET and SVOUT . – (See the Applications Information section.) Note that the respect to SVOUT , a VINREG control loop servos COMPa synchronization range of CLKIN is approximately ±40% so as to decrease the power inductor current and thus – of the oscillator frequency programmed by the f regulate VINREG at 2V with respect to SV . See the SET pin. OUT Applications Information section.
CLKIN (B1):
Oscillator Synchronization Input. Leave CLKIN open circuit for forced continuous mode operation. If this input voltage regulation feature is not desired, con- nect VINREG to INTVCC. Alternatively, this pin can be driven so as to synchronize the switching frequency of the LTM4651 to a clock signal. In
TEMP+ (J1, J6):
Temperature Sensor, Positive Input. this condition, the LTM4651 operates in forced-continuous Emitter of a 2N3906-genre PNP bipolar junction transistor mode and the cycle-by-cycle turn-on of the Primary MOS- (BJT). Optionally interface to temperature monitoring cir- FET is coincident with the rising edge of the clock applied cuitry such as LTC®2997, LTC2990, LTC2974 or LTC2975. to CLKIN. Note the synchronization range of CLKIN is ap- Otherwise leave electrically open. Pins J1 and J6 are proximately ±40% of the oscillator frequency programmed electrically connected together internal to the LTM4651, by the f and thus it is only necessary to connect one TEMP+ pin SET pin. See the Applications Information section. to monitoring circuitry. The remaining TEMP+ pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Test Circuit Decoupling Requirements Operation Applications Information Typical Applications Package Photograph Package Description Typical Application Related Parts
PIN FUNCTIONS
In addition, the output of the LTM4651 can track a voltage
COMPa (E2):
Current Control Threshold and Error Ampli- applied between the ISETa pin and the SV – OUT pins. See fier Compensation Node. The trip threshold of LTM4651’s the Applications Information section. current comparator increases with a respective rise in
PGOOD (D1):
Power Good Indicator, Open-Drain Output COMPa voltage. A small filter capacitor (10pF) internal Pin. PGOOD is high impedance when PGDFB – SV – to the LTM4651 on this pin introduces a high-frequency OUT is within approximately ±7.5% of 0.6V. PGOOD is pulled to roll-off of the error-amplifier response, yielding good noise GND when PGDFB – SV – rejection in the control-loop. COMPa is usually electrically OUT is outside this range. connected to COMPb in one’s application, thus applying
PGDFB (D2):
Power Good Feedback Programming Pin. default loop compensation. Loop compensation (a series Connect PGDFB to GNDSNS through a resistor, RPGDFB. resistor-capacitor) can be applied externally to COMPa if R – PGDFB configures the voltage threshold of VOUT for desired or needed, instead. See COMPb. which PGOOD toggles its state. If the PGOOD feature is used, set R
COMPb (E1):
Internal Loop Compensation Network. PGDFB to: For a majority of applications, the internal, default loop ⎛ ⎞ ⎜ | V – | compensation of the LTM4651 is suitable to apply “as is” R OUT ⎟ PGDFB = ⎜ – 1 • 4.99k ⎜ 0.6V ⎟⎟ and yields very satisfactory results: apply the default loop ⎝ ⎠ compensation to the control loop by simply connecting COMPa to COMPb. When more specialized applications otherwise, leave PGDFB open circuit. require a personal touch to the optimization of control loop A small filter capacitor (220pF) internal to the LTM4651 response, this can be accomplished by connecting a series – on this pin provides high frequency noise immunity for resistor-capacitor network from COMPa to SVOUT —and the PGOOD output indicator. leaving COMPb open circuit.
f VINREG (D3):
Input Voltage Regulation Programming Pin.
SET (E3):
Oscillator Frequency Programming Pin. The default switching frequency of the LTM4651 is 400kHz. Optionally connect this pin to the midpoint node formed – Often, it is necessary to increase the programmed fre- by a resistor-divider between VD and SVOUT . When the quency by connecting a resistor between f – voltage on VINREG falls below approximately 2V with SET and SVOUT . – (See the Applications Information section.) Note that the respect to SVOUT , a VINREG control loop servos COMPa synchronization range of CLKIN is approximately ±40% so as to decrease the power inductor current and thus – of the oscillator frequency programmed by the f regulate VINREG at 2V with respect to SV . See the SET pin. OUT Applications Information section.
CLKIN (B1):
Oscillator Synchronization Input. Leave CLKIN open circuit for forced continuous mode operation. If this input voltage regulation feature is not desired, con- nect VINREG to INTVCC. Alternatively, this pin can be driven so as to synchronize the switching frequency of the LTM4651 to a clock signal. In
TEMP+ (J1, J6):
Temperature Sensor, Positive Input. this condition, the LTM4651 operates in forced-continuous Emitter of a 2N3906-genre PNP bipolar junction transistor mode and the cycle-by-cycle turn-on of the Primary MOS- (BJT). Optionally interface to temperature monitoring cir- FET is coincident with the rising edge of the clock applied cuitry such as LTC®2997, LTC2990, LTC2974 or LTC2975. to CLKIN. Note the synchronization range of CLKIN is ap- Otherwise leave electrically open. Pins J1 and J6 are proximately ±40% of the oscillator frequency programmed electrically connected together internal to the LTM4651, by the f and thus it is only necessary to connect one TEMP+ pin SET pin. See the Applications Information section. to monitoring circuitry. The remaining TEMP+ pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Test Circuit Decoupling Requirements Operation Applications Information Typical Applications Package Photograph Package Description Typical Application Related Parts