Datasheet AD8284 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Radar Receive Path AFE: 4-Channel MUX with LNA, PGA, AAF, and ADC |
| Seiten / Seite | 28 / 10 — AD8284. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 35dB. 29dB. … |
| Revision | D |
| Dateiformat / Größe | PDF / 640 Kb |
| Dokumentensprache | Englisch |
AD8284. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 35dB. 29dB. 23dB. √Hz. 17dB. IN GA. ISE ( O. –20. –40. –60. 0.1. 100. FREQUENCY (MHz). 210. 180
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AD8284 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, TA = 25°C, fS = 60 MSPS, RIN = 200 kΩ, VREF = 1.0 V.
60 10 9 35dB 29dB 40 8 7 20 ) ) 23dB 6 B √Hz d 17dB V/ ( 0 n 5 17dB IN GA ISE ( O 4 –20 N 23dB 3 2 –40 1 35dB 29dB –60 0 0.1 1 10 100
04 0
0.1 1 10
-007
FREQUENCY (MHz)
0992-
FREQUENCY (MHz)
1 10992 Figure 4. Channel Gain vs. Frequency Figure 7. Short-Circuit Input Referred Noise vs. Frequency
30 210 20 180 10 S 150 T ) HI B 0 F d 120 ( R O IN E –10 B GA 90 NUM –20 60 –30 30 00 08 10 18 20 28 30 38 40 80 88 90 98 A0 A8 B0 B8 C0 0 –40 16.8 17.0 17.2 17.4 17.6 1 10 50
-008 -005
CODE FREQUENCY (MHz)
10992 10992 Figure 5. Gain Histogram (Gain = 17 dB) Figure 8. Filter Frequency Response
200 350 180 160 300 140 ) S 250 35dB IT 120 √Hz H F V/ 200 n 100 O R E ISE ( B O 80 M 150 N 29dB NU 60 100 40 50 20 23dB 17dB 0 0 0.1 1 10
-009
28.5 28.8 29.1 29.4 29.7 30.0
-006
FREQUENCY (MHz) CODE
10992 10992 Figure 9. Short-Circuit Output Referred Noise vs. Frequency Figure 6. Gain Histogram (Gain = 29 dB) Rev. D | Page 10 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products
AVDD18x = 1.8 V, AVDD33x = 3.3 V, TA = 25°C, fS = 60 MSPS, RIN = 200 kΩ, VREF = 1.0 V.
60 10 9 35dB 29dB 40 8 7 20 ) ) 23dB 6 B √Hz d 17dB V/ ( 0 n 5 17dB IN GA ISE ( O 4 –20 N 23dB 3 2 –40 1 35dB 29dB –60 0 0.1 1 10 100
04 0
0.1 1 10
-007
FREQUENCY (MHz)
0992-
FREQUENCY (MHz)
1 10992 Figure 4. Channel Gain vs. Frequency Figure 7. Short-Circuit Input Referred Noise vs. Frequency
30 210 20 180 10 S 150 T ) HI B 0 F d 120 ( R O IN E –10 B GA 90 NUM –20 60 –30 30 00 08 10 18 20 28 30 38 40 80 88 90 98 A0 A8 B0 B8 C0 0 –40 16.8 17.0 17.2 17.4 17.6 1 10 50
-008 -005
CODE FREQUENCY (MHz)
10992 10992 Figure 5. Gain Histogram (Gain = 17 dB) Figure 8. Filter Frequency Response
200 350 180 160 300 140 ) S 250 35dB IT 120 √Hz H F V/ 200 n 100 O R E ISE ( B O 80 M 150 N 29dB NU 60 100 40 50 20 23dB 17dB 0 0 0.1 1 10
-009
28.5 28.8 29.1 29.4 29.7 30.0
-006
FREQUENCY (MHz) CODE
10992 10992 Figure 9. Short-Circuit Output Referred Noise vs. Frequency Figure 6. Gain Histogram (Gain = 29 dB) Rev. D | Page 10 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products