Datasheet AD8284 (Analog Devices)

HerstellerAnalog Devices
BeschreibungRadar Receive Path AFE: 4-Channel MUX with LNA, PGA, AAF, and ADC
Seiten / Seite28 / 1 — Radar Receive Path AFE: 4-Channel Mux. with LNA, PGA, AAF, and ADC. Data …
RevisionD
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DokumentenspracheEnglisch

Radar Receive Path AFE: 4-Channel Mux. with LNA, PGA, AAF, and ADC. Data Sheet. AD8284. FEATURES. FUNCTIONAL BLOCK DIAGRAM

Datasheet AD8284 Analog Devices, Revision: D

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Radar Receive Path AFE: 4-Channel Mux with LNA, PGA, AAF, and ADC Data Sheet AD8284 FEATURES FUNCTIONAL BLOCK DIAGRAM 4-channel mux to LNA, PGA, AAF O ] T ] 1 direct-to-ADC channel N G X[1 X[0 DD18 DD33 AS DD18 DD33x EF Programmable gain amplifier (PGA) SEL DW FLA Z MU MU AV AV P S DV DV VR RBI Includes low noise preamplifier (LNA) SPI-programmable gain = 17 dB to 35 dB in 6 dB steps REFERENCE Antialiasing filter (AAF) INA+ Programmable third-order low-pass elliptic filter (LPF) from INA– AD8284 SATURATION 9 MHz to 15 MHz DETECTION INB+ Analog-to-digital converter (ADC) INB– 12 bits of accuracy of up to 60 MSPS MUX LNA PGA AAF SNR = 67 dB INC+ SFDR = 68 dBc INC– D0 Low power, 345 mW at 12 bits per 60 MSPS 12-BIT IND+ MUX TO ADC D11 Low noise, 3.5 nV/√Hz maximum of input referred IND– voltage noise INADC+ Power-down mode INADC– 64-lead, 10 mm × 10 mm TQFP package Specified from −40°C to +105°C Qualified for automotive applications SPI APPLICATIONS K
001
Automotive radar CS DI K+ K– S DO CL S AUX S CL CL
10992-
Adaptive cruise control
Figure 1.
Collision avoidance Blind spot detection Self parking Electronic bumper GENERAL DESCRIPTION
The AD8284 is an integrated analog front end designed for low for dynamic performance and low power in applications where cost, compact size, flexibility, and ease of use. It contains a a small package size is critical. 4-channel differential multiplexer (mux), a 1-channel low noise Fabricated in an advanced CMOS process, the AD8284 is available preamplifier (LNA) with a programmable gain amplifier (PGA) in a 10 mm × 10 mm, RoHS compliant, 64-lead TQFP. It is speci- and an antialiasing filter (AAF), as well as one direct-to-ADC fied over the automotive temperature range of −40°C to +105°C. channel, al integrated with a single, 12-bit analog-to-digital converter (ADC). The AD8284 also incorporates a saturation
Table 1. Related Devices
detection circuit for high frequency overvoltage conditions that
Part No. Description
would otherwise be filtered by the AAF. AD8285 4-Channel LNA/PGA/AAF, pseudosimultaneous The analog channel features a gain range of 17 dB to 35 dB in channel sampling with ADC 6 dB increments, and an ADC with a conversion rate of up to AD8283 6-Channel LNA/PGA/AAF, pseudosimultaneous channel sampling with ADC 60 MSPS. The combined input referred voltage noise of the entire ADA8282 4-Channel LNA/PGA channel is 3.5 nV/√Hz at maximum gain. The channel is optimized
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products