X9418 Datasheet (Renesas) - 5
| Hersteller | Renesas |
| Beschreibung | Low Noise/Low Power/2-Wire Bus |
| Seiten / Seite | 20 / 5 — Figure 2. Instruction Byte Format. Figure 3. Two-Byte Instruction Sequence |
| Revision | 2.00 |
| Dateiformat / Größe | PDF / 841 Kb |
| Dokumentensprache | Englisch |
Figure 2. Instruction Byte Format. Figure 3. Two-Byte Instruction Sequence
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Figure 2. Instruction Byte Format
or it may occur globally, wherein the transfer occurs between both of the potentiometers and one of their Register associated registers. Select Four instructions require a three-byte sequence to complete. These instructions transfer data between the I3 I2 I1 I0 R1 R0 0 P0 host and the X9418; either between the host and one of the Data Registers or directly between the host and the Instructions Wiper Counter wiper counter register. These instructions are: Read Register Select Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register The four high order bits define the instruction. The next (change current wiper position of the selected pot), read two bits (R1 and R0) select one of the four registers that Data Register (read the contents of the selected is to be acted upon when a register oriented instruction nonvolatile register) and write Data Register (write a new is issued. The last bits (P0) select which one of the two value to the selected Data Register). The sequence of potentiometers is to be affected by the instruction. Bit 1 operations is shown in Figure 4. is defined to be 0. The Increment/Decrement command is different from Four of the nine instructions end with the transmission of the other commands. Once the command is issued and the instruction byte. The basic sequence is illustrated in the X9418 has responded with an acknowledge, the Figure 3. These two-byte instructions exchange data master can clock the selected wiper up and/or down in between the wiper counter register and one of the data one segment steps; thereby, providing a fine tuning registers. A transfer from a Data Register to a Wiper capability to the host. For each SCL clock pulse (tHIGH) Counter Register is essentially a write to a static RAM. while SDA is HIGH, the selected wiper will move one The response of the wiper to this action will be delayed resistor segment towards the VH/RH terminal. Similarly, tWRL. A transfer from the wiper counter register (current for each SCL clock pulse while SDA is LOW, the wiper position), to a Data Register is a write to selected wiper will move one resistor segment towards nonvolatile memory and takes a minimum of tWR to the VL/RL terminal. A detailed illustration of the complete. The transfer can occur between one of the sequence and timing for this operation are shown in two potentiometers and one of its associated registers; Figures 5 and 6 respectively.
Figure 3. Two-Byte Instruction Sequence
SCL SDA S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 R1 R0 0 P0 A S T C C T A K K O R P T FN8194 Rev 2.00 Page 5 of 20 October 12, 2006
Figure 2. Instruction Byte Format
or it may occur globally, wherein the transfer occurs between both of the potentiometers and one of their Register associated registers. Select Four instructions require a three-byte sequence to complete. These instructions transfer data between the I3 I2 I1 I0 R1 R0 0 P0 host and the X9418; either between the host and one of the Data Registers or directly between the host and the Instructions Wiper Counter wiper counter register. These instructions are: Read Register Select Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register The four high order bits define the instruction. The next (change current wiper position of the selected pot), read two bits (R1 and R0) select one of the four registers that Data Register (read the contents of the selected is to be acted upon when a register oriented instruction nonvolatile register) and write Data Register (write a new is issued. The last bits (P0) select which one of the two value to the selected Data Register). The sequence of potentiometers is to be affected by the instruction. Bit 1 operations is shown in Figure 4. is defined to be 0. The Increment/Decrement command is different from Four of the nine instructions end with the transmission of the other commands. Once the command is issued and the instruction byte. The basic sequence is illustrated in the X9418 has responded with an acknowledge, the Figure 3. These two-byte instructions exchange data master can clock the selected wiper up and/or down in between the wiper counter register and one of the data one segment steps; thereby, providing a fine tuning registers. A transfer from a Data Register to a Wiper capability to the host. For each SCL clock pulse (tHIGH) Counter Register is essentially a write to a static RAM. while SDA is HIGH, the selected wiper will move one The response of the wiper to this action will be delayed resistor segment towards the VH/RH terminal. Similarly, tWRL. A transfer from the wiper counter register (current for each SCL clock pulse while SDA is LOW, the wiper position), to a Data Register is a write to selected wiper will move one resistor segment towards nonvolatile memory and takes a minimum of tWR to the VL/RL terminal. A detailed illustration of the complete. The transfer can occur between one of the sequence and timing for this operation are shown in two potentiometers and one of its associated registers; Figures 5 and 6 respectively.
Figure 3. Two-Byte Instruction Sequence
SCL SDA S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 R1 R0 0 P0 A S T C C T A K K O R P T FN8194 Rev 2.00 Page 5 of 20 October 12, 2006