Datasheet ATtiny13, ATtiny13V - Summary (Microchip) - 4

2. Overview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed.
2.1 Block Diagram Figure 2-1.
Block Diagram 8-BIT DATABUS STACK CALIBRATED POINTER INTERNAL WATCHDOG OSCILLATOR OSCILLATOR SRAM WATCHDOG TIMING AND VCC TIMER CONTROL PROGRAM MCU CONTROL REGISTER COUNTER MCU STATUS GND REGISTER PROGRAM FLASH TIMER/ COUNTER0 INSTRUCTION GENERAL REGISTER PURPOSE INTERRUPT UNIT REGISTERS X PROGRAMMING INSTRUCTION Y LOGIC DECODER Z CONTROL DATA LINES ALU EEPROM STATUS REGISTER ADC / DATA REGISTER DATA DIR. ANALOG COMPARATOR PORT B REG.PORT B PORT B DRIVERS RESET CLKI PB0-PB5
4 ATtiny13
2535JS–AVR–08/10 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Data Retention 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 7. Packaging Information 7.1 8P3 7.2 8S2 7.3 S8S1 7.4 20M1 7.5 10M1 8. Errata 8.1 ATtiny13 Rev. D 8.2 ATtiny13 Rev. C 8.3 ATtiny13 Rev. B 8.3.1 Wrong values read after Erase Only operation 8.3.2 High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail 8.3.3 Device may lock for further programming 8.3.4 debugWIRE communication not blocked by lock-bits 8.3.5 Watchdog Timer Interrupt disabled 8.3.6 EEPROM can not be written below 1.9 Volt 8.4 ATtiny13 Rev. A 9. Datasheet Revision History 9.1 Rev. 2535J-08/10 9.2 Rev. 2535I-05/08 9.3 Rev. 2535H-10/07 9.4 Rev. 2535G-01/07 9.5 Rev. 2535F-04/06 9.6 Rev. 2535E-10/04 9.7 Rev. 2535D-04/04 9.8 Rev. 2535C-02/04 9.9 Rev. 2535B-01/04 9.10 Rev. 2535A-06/03