Datasheet Nanjing Qinheng Microelectronics CH32X035 — Datenblatt

CH32X035/X033 Datasheet
V2.3
https://wch-ic.com Overview
CH32X035 is an industrial-grade microcontroller based on the QingKe RISC-V core. CH32X035 has built-in USB
and PD PHY, supports USB Host and USB Device functions, PDUSB and Type-C fast charging functions, built-in
programmable protocol I/O controller, provides 2 groups of OPA, 3 groups of CMP, 4 groups of USART, I2C, SPI,
multiple timers, 12-bit ADC, 14-channel Touchkey and other rich peripheral resources. Features Core
-QingKe 32-bit RISC-V4C core
-Support RV32IMAC instruction set and selfextending instructions
-Fast programmable interrupt controller +
hardware interrupt stack -Branch prediction, conflict handling mechanism
-Single-cycle multiplication, hardware division Memory
-20KB volatile data storage area SRAM
-62KB program memory area CodeFlash
-256B system non-volatile configuration
information memory area -256B user-defined information storage area Power management and low-power:
-System power supply VDD voltage range:
2V~5.5V -Low power modes: Sleep, Stop, Standby
System clock & Reset
-Built-in 48MHz RC oscillator
-Power on/down reset, programmable voltage
detector
8-channel general-purpose DMA controller …

CH32X035 Reference Manual
V1.9
https://wch-ic.com Overview
CH32X035 is an industrial-grade microcontroller based on the QingKe RISC-V core. CH32X035 has built-in fullspeed USB and USB PD PHY, supports USB Host and USB Device functions, USB PD and type C fast charging
functions, built-in programmable protocol I/O controller (PIOC), provides 2 OPAs, 3 CMPs, 4 USARTs, I2C, SPI,
multiple timers, 12-bit ADC, 14-channel touch-key, etc.
This manual provides detailed information on the use of the CH32X035 product for the development of user
applications.
Please refer to the following datasheet for device characteristics of this family: CH32X035DS0.
For information about the RISC-V core, please refer to the following: QingKeV4_Processor_Manual.
RISC-V core version comparison overview
Hardware Interrupt
Features
Instruction
Core
stack
nesting
set
versions
levels
levels
QingKeV4B
QingKeV4C …