Datasheet GigaDevice GD32E103R8T7 — Datenblatt

GigaDevice Semiconductor Inc.
GD32E103xx
Arm® Cortex®-M4 32-bit MCU Datasheet
Revision 1.15
( Dec. 2024 ) GD32E103xx Datasheet Table of Contents
Table of Contents . 1
List of Figures . 4
List of Tables . 5
1. General description . 7
2. Device overview . 8
2.1. Device information . 8 2.2. Block diagram . 9 2.3. Pinouts and pin assignment . 10 2.4. Memory map . 12 2.5. Clock tree . 16 2.6. Pin definitions . 16 2.6.1. GD32E103Vx LQFP100 pin definitions . 17 2.6.2. GD32E103Rx LQFP64 pin definitions . 23 2.6.3. GD32E103Cx LQFP48 pin definitions . 27 2.6.4. GD32E103Tx QFN36 pin definitions . 30 3. Functional description . 33
3.1. Arm® Cortex®-M4 core . 33 3.2. On-chip memory . 33 3.3. Clock, reset and supply management . 34 3.4. Boot modes . 34 3.5. Power saving modes . 35 3.6. Analog to digital converter (ADC) . 35 3.7. Digital to analog converter (DAC) . 36 3.8. DMA . 36 3.9. General-purpose inputs/outputs (GPIOs) . 36 3.10. Timers and PWM generation . 37 3.11. Real time clock (RTC) . 38 3.12. Inter-integrated circuit (I2C) . 38 3.13. Serial peripheral interface (SPI) . 38 3.14. Universal synchronous asynchronous receiver transmitter (USART) . 39
1 GD32E103xx Datasheet
3.15. Inter-IC sound (I2S) . 39 3.16. Universal serial bus full-speed interface (USBFS) . 39 3.17. External memory controller (EXMC) . 40 3.18. Debug mode . 40 3.19. Package and operation temperature . 40 4. Electrical characteristics . 41
4.1. Absolute maximum ratings . 41 4.2. Operating conditions characteristics . 42 4.3. Power consumption . 43 4.4. EMC characteristics . 50 4.5. Power supply supervisor characteristics . 51 4.6. Electrical sensitivity . 52 4.7. External clock characteristics . 53 4.8. Internal clock characteristics . 55 4.9. PLL characteristics. 56 4.10. Memory characteristics . 57 4.11. NRST pin characteristics . 57 4.12. GPIO characteristics . 58 4.13. ADC characteristics . 60 4.14. Temperature sensor characteristics . 61 4.15. DAC characteristics . 61 4.16. I2C characteristics . 63 4.17. SPI characteristics . 64 4.18. I2S characteristics. 65 4.19. USART characteristics . 67 4.20. USBFS characteristics . 67 4.21. EXMC characteristics. 68 4.22. TIMER characteristics . 72 4.23. WDGT characteristics . 72 4.24. Parameter conditions. 73 5. Package information. 74
5.1. LQFP100 package outline dimensions. 74
2 GD32E103xx Datasheet
5.2. LQFP64 package outline dimensions. 76 5.3. LQFP48 package outline dimensions. 78 5.4. QFN36 package outline dimensions . 80 5.5. Thermal characteristics . 82 6. Ordering information . 84
7. Revision history . 85 3 GD32E103xx Datasheet List of Figur …

GigaDevice Semiconductor Inc.
GD32E10x
ARM® Cortex®-M4 32-bit MCU
For GD32E103xx User Manual
Revision 2.1
( Feb. 2025 ) GD32E10x User Manual Table of Contents
Table of Contents . 2
List of Figures . 14
List of Tables . 20
1. System and memory architecture . 22
1.1. ARM Cortex-M4 processor . 22 1.2. System architecture . 23 1.3. Memory map . 25 1.3.1. Bit-banding . 29 1.3.2. On-chip SRAM memory . 30 1.3.3. On-chip flash memory overview . 30 1.4. Boot configuration. 30 1.5. Device electronic signature . 31 1.5.1. Memory density information . 32 1.5.2. Unique device ID (96 bits) . 32 1.6. System configuration registers . 33 2. Flash memory controller (FMC) . 34
2.1. Overview . 34 2.2. Characteristics. 34 2.3. Function overview . 34 2.3.1. Flash memory architecture . 34 2.3.2. Read operations . 35 2.3.3. Unlock the FMC_CTL register . 36 2.3.4. Page erase. 37 2.3.5. Mass erase . 38 2.3.6. Main flash programming . 39 2.3.7. OTP programming . 41 2.3.8. Option bytes Erase . 42 2.3.9. Option bytes modify . 42 2.3.10. Option bytes description . 43 2.3.11. Page erase/program protection . 44 2.3.12. Security protection . 44 2.4. Register definition . 45 2.4.1. Wait state register (FMC_WS) . 45 2.4.2. Unlock key register (FMC_KEY) . 46 2.4.3. Option byte unlock key register (FMC_OBKEY) . 46
2 GD32E10x User Manual
2.4.4. Status register (FMC_STAT) . 47 2.4.5. Control register (FMC_CTL) . 47 2.4.6. Address register (FMC_ADDR) . 49 2.4.7. Option byte status register (FMC_OBSTAT). 49 2.4.8. Erase/Program protection register (FMC_WP) . 50 2.4.9. Product ID register (FMC_PID). 50 3. Power management unit (PMU) . 52
3.1. Overview . 52 3.2. Characteristics. 52 3.3. Function overview . 52 3.3.1. Backup domain . 53 3.3.2. VDD / VDDA power domain . 54 3.3.3. 1.2V power domain . 56 3.3.4. Power saving modes . 56 3.4. Register definition . 59 3.4.1. Control register (PMU_CTL) . 59 3.4.2. Control and status register (PMU_CS) . 60 4. Backup unit (BKP) . 62
4.1. Overview . 62 4.2. Characteristics. 62 4.3. Function overview . 62 4.3.1. RTC clock calibration . 62 4.3.2. Tamper detection . 62 4.4. Register definition . 64 4.4.1. Backup data register x (BKP_DATAx) (x= 0.41) . 64 4.4.2. RTC signal output control register (BKP_OCTL) . 64 4.4.3. Tamper pin control register (BKP_TPCTL) . 65 4.4.4. Tamper control and status register (BKP_TPCS) . 66 5. Reset and clock unit (RCU) . 67
5.1. Reset control unit (RCTL) . 67 5.1.1. Overview . 67 5.1.2. Function overview . 67 5.2. Clock control unit (CCTL) . 68 5.2.1. Overview . 68 5.2.2. Characteristics . 70 5.2.3. Function overview . 70 5.3. Regis …