Datasheet Texas Instruments SN74LVTH126 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH126
Datasheet Texas Instruments SN74LVTH126

3,3-V-ABT-Vierfachbuspuffer mit 3-Zustands-Ausgängen

Datenblätter

SN54LVTH126, SN74LVTH126 datasheet
PDF, 722 Kb, Revision: B, Datei veröffentlicht: Oct 10, 2003
Auszug aus dem Dokument

Preise

Status

SN74LVTH126DSN74LVTH126DBRSN74LVTH126DGVRSN74LVTH126DRSN74LVTH126DRG4SN74LVTH126NSRSN74LVTH126PWSN74LVTH126PWG4SN74LVTH126PWRSN74LVTH126PWRE4SN74LVTH126PWRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNoNo

Verpackung

SN74LVTH126DSN74LVTH126DBRSN74LVTH126DGVRSN74LVTH126DRSN74LVTH126DRG4SN74LVTH126NSRSN74LVTH126PWSN74LVTH126PWG4SN74LVTH126PWRSN74LVTH126PWRE4SN74LVTH126PWRG4
N1234567891011
Pin1414141414141414141414
Package TypeDDBDGVDDNSPWPWPWPWPW
Industry STD TermSOICSSOPTVSOPSOICSOICSOPTSSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY50200020002500250020009090200020002000
CarrierTUBELARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&R
Device MarkingLVTH126LXH126LXH126LVTH126LVTH126LVTH126LXH126LXH126LXH126LXH126LXH126
Width (mm)3.915.34.43.913.915.34.44.44.44.44.4
Length (mm)8.656.23.68.658.6510.355555
Thickness (mm)1.581.951.051.581.581.9511111
Pitch (mm)1.27.65.41.271.271.27.65.65.65.65.65
Max Height (mm)1.7521.21.751.7521.21.21.21.21.2
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Parameter

Parameters / ModelsSN74LVTH126D
SN74LVTH126D
SN74LVTH126DBR
SN74LVTH126DBR
SN74LVTH126DGVR
SN74LVTH126DGVR
SN74LVTH126DR
SN74LVTH126DR
SN74LVTH126DRG4
SN74LVTH126DRG4
SN74LVTH126NSR
SN74LVTH126NSR
SN74LVTH126PW
SN74LVTH126PW
SN74LVTH126PWG4
SN74LVTH126PWG4
SN74LVTH126PWR
SN74LVTH126PWR
SN74LVTH126PWRE4
SN74LVTH126PWRE4
SN74LVTH126PWRG4
SN74LVTH126PWRG4
Bits44444444444
F @ Nom Voltage(Max), Mhz160160160160160160160160160160160
ICC @ Nom Voltage(Max), mA0.0070.0070.0070.0070.0070.0070.0070.0070.0070.0070.007
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64
Package GroupSOICSSOPTVSOPSOICSOICSOTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG14SOIC: 52 mm2: 6 x 8.65(SOIC)14SSOP: 48 mm2: 7.8 x 6.2(SSOP)14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SO: 80 mm2: 7.8 x 10.2(SO)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.63.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.72.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.33.33.3
tpd @ Nom Voltage(Max), ns3.93.93.93.93.93.93.93.93.93.93.9

Öko-Plan

SN74LVTH126DSN74LVTH126DBRSN74LVTH126DGVRSN74LVTH126DRSN74LVTH126DRG4SN74LVTH126NSRSN74LVTH126PWSN74LVTH126PWG4SN74LVTH126PWRSN74LVTH126PWRE4SN74LVTH126PWRG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver