Datasheet Texas Instruments SN74LVTH126PWRE4 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH126
ArtikelnummerSN74LVTH126PWRE4
Datasheet Texas Instruments SN74LVTH126PWRE4

3,3-V-ABT-Vierfachbuspuffer mit 3-Zustands-Ausgängen 14-TSSOP -40 bis 85

Datenblätter

SN54LVTH126, SN74LVTH126 datasheet
PDF, 722 Kb, Revision: B, Datei veröffentlicht: Oct 10, 2003
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin14
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLXH126
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataHerunterladen

Parameter

Bits4
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)0.007 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)-32/64 mA
Package GroupTSSOP
Package Size: mm2:W x L14TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V
tpd @ Nom Voltage(Max)3.9 ns

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver