Datasheet Texas Instruments SN74HC112DT — Datenblatt

HerstellerTexas Instruments
SerieSN74HC112
ArtikelnummerSN74HC112DT
Datasheet Texas Instruments SN74HC112DT

Dual JK Negative-Edge-Triggered Flip-Flops mit klarem und voreingestelltem 16-SOIC -40 bis 85

Datenblätter

SN54HC112, SN74HC112 datasheet
PDF, 598 Kb, Revision: F, Datei veröffentlicht: Sep 26, 2003
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin16
Package TypeD
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY250
CarrierSMALL T&R
Device MarkingHC112
Width (mm)3.91
Length (mm)9.9
Thickness (mm)1.58
Pitch (mm)1.27
Max Height (mm)1.75
Mechanical DataHerunterladen

Parameter

Bits2
F @ Nom Voltage(Max)70 Mhz
ICC @ Nom Voltage(Max)0.04 mA
Output Drive (IOL/IOH)(Max)-4/4 mA
Package GroupSOIC
Package Size: mm2:W x L16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyHC
VCC(Max)6 V
VCC(Min)2 V
Voltage(Nom)3.3,5 V
tpd @ Nom Voltage(Max)41 ns

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • HCMOS Design Considerations (Rev. A)
    PDF, 207 Kb, Revision: A, Datei veröffentlicht: Sep 9, 2002
    This document describes a potential problem designers may encounter when using high-speed CMOS (HC) logic devices. There also is a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered. The design engineer inevitably encounters these interfaces. Key considerations for handling these interfaces are also discussed in this book.

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop