Datasheet Texas Instruments SN74F112NSR — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN74F112 |
| Artikelnummer | SN74F112NSR |
Dual JK Negative-Edge-Triggered Flip-Flop mit Clear und Preset 16-SO 0 bis 70
Datenblätter
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset datasheet
PDF, 639 Kb, Revision: A, Datei veröffentlicht: Oct 1, 1993
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 16 |
| Package Type | NS |
| Industry STD Term | SOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | 74F112 |
| Width (mm) | 5.3 |
| Length (mm) | 10.3 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2 |
| Mechanical Data | Herunterladen |
Parameter
| Bits | 2 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 19 mA |
| Output Drive (IOL/IOH)(Max) | -1/20 mA |
| Package Group | SO |
| Package Size: mm2:W x L | 16SO: 80 mm2: 7.8 x 10.2(SO) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | F |
| VCC(Max) | 5.5 V |
| VCC(Min) | 4.5 V |
| Voltage(Nom) | 5 V |
| tpd @ Nom Voltage(Max) | 7.5 ns |
Öko-Plan
| RoHS | Compliant |
Modellreihe
Serie: SN74F112 (9)
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop