Datasheet Texas Instruments CDC2536 — Datenblatt

HerstellerTexas Instruments
SerieCDC2536
Datasheet Texas Instruments CDC2536

3,3-V-PLL-Takttreiber mit 1 / 2x-, 1x- und 2x-Frequenzoptionen

Datenblätter

CDC2536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 446 Kb, Revision: E, Datei veröffentlicht: Jul 9, 2004
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Preise

Status

CDC2536DBCDC2536DBG4CDC2536DBRCDC2536DBRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoYesNo

Verpackung

CDC2536DBCDC2536DBG4CDC2536DBRCDC2536DBRG4
N1234
Pin28282828
Package TypeDBDBDBDB
Industry STD TermSSOPSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY505020002000
CarrierTUBETUBELARGE T&RLARGE T&R
Device MarkingCDC2536CDC2536CDC2536CDC2536
Width (mm)5.35.35.35.3
Length (mm)10.210.210.210.2
Thickness (mm)1.951.951.951.95
Pitch (mm).65.65.65.65
Max Height (mm)2222
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsCDC2536DB
CDC2536DB
CDC2536DBG4
CDC2536DBG4
CDC2536DBR
CDC2536DBR
CDC2536DBRG4
CDC2536DBRG4
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps200200200200
Number of Outputs6666
Operating Frequency Range(Max), MHz100100100100
Operating Frequency Range(Min), MHz25252525
Package GroupSSOPSSOPSSOPSSOP
Package Size: mm2:W x L, PKG28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
RatingCatalogCatalogCatalogCatalog
VCC, V3.33.33.33.3
t(phase error), ps500500500500
tsk(o), ps500500500500

Öko-Plan

CDC2536DBCDC2536DBG4CDC2536DBRCDC2536DBRG4
RoHSCompliantCompliantCompliantCompliant

Anwendungshinweise

  • Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers
    PDF, 101 Kb, Datei veröffentlicht: Apr 1, 1996
    Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo

Modellreihe

Herstellerklassifikation

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers