Datasheet Texas Instruments LMK04208NKDR — Datenblatt

Product
Folder Sample &
Buy Support &
Community Tools &
Software Technical
Documents LMK04208
SNAS684 – SEPTEMBER 2016 LMK04208 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1 Features 3 Description The LMK04208 is a high performance clock
conditioner with superior clock jitter cleaning,
generation, and distribution with advanced features to
meet next generation system requirements. The dual
loop PLLatinumв„ў architecture is capable of 111 fs,
RMS jitter (12 kHz to 20 MHz) using a low-noise
VCXO module or sub-200 fs rms jitter (12 kHz to 20
MHz) using a low cost external crystal and varactor
diode. 1 2 Ultra-Low RMS Jitter Performance
– 111 fs, RMS Jitter (12 kHz to 20 MHz)
– 123 fs, RMS Jitter (100 Hz to 20 MHz)
Dual Loop PLLatinumв„ў PLL Architecture
PLL1
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode when Input Clocks are Lost
– Automatic or Manual Triggering/Recovery …