Datasheet Texas Instruments SN74LVTH16374DLR — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH16374
ArtikelnummerSN74LVTH16374DLR
Datasheet Texas Instruments SN74LVTH16374DLR

3,3-V-ABT-16-Bit-Flip-Flops vom Typ D-Typ mit 3-Zustands-Ausgängen 48-SSOP -40 bis 85

Datenblätter

3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet
PDF, 766 Kb, Revision: R, Datei veröffentlicht: Aug 23, 2007
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin48
Package TypeDL
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY1000
CarrierLARGE T&R
Device MarkingLVTH16374
Width (mm)7.49
Length (mm)15.88
Thickness (mm)2.59
Pitch (mm).635
Max Height (mm)2.79
Mechanical DataHerunterladen

Parameter

3-State OutputYes
Bits16
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)5 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupSSOP
Package Size: mm2:W x L48SSOP: 164 mm2: 10.35 x 15.88(SSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V
tpd @ Nom Voltage(Max)4.5 ns

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop