Datasheet SN74LVC1G74 (Texas Instruments) - 9
| Hersteller | Texas Instruments |
| Beschreibung | Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset datasheet |
| Seiten / Seite | 24 / 9 — SN74LVC1G74. www.ti.com. 9 Detailed Description. 9.1 Overview. 9.2 … |
| Revision | E |
| Dateiformat / Größe | PDF / 1.4 Mb |
| Dokumentensprache | Englisch |
SN74LVC1G74. www.ti.com. 9 Detailed Description. 9.1 Overview. 9.2 Functional Block Diagram. PRE. CLK. CLR. 9.3 Feature Description
Textversion des Dokuments
SN74LVC1G74 www.ti.com
SCES794E – OCTOBER 2009 – REVISED JANUARY 2015
9 Detailed Description 9.1 Overview
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram 7 PRE 1 C CLK C C 5 Q TG C C C C 2 D TG TG TG 3 Q C C C 6 CLR 9.3 Feature Description
• Allow down voltage translation – 5 V to 3.3 V – 5.0 V to 1.8 V – 3.3 V to 1.8 V • Inputs accept voltage levels up to 5.5 V • Ioff Feature – Can prevent backflow current that can damage device when powered down
9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUTS PRE CLR CLK D Q Q
L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC1G74 Document Outline 1 Features 2 Applications 3 Description 4 Simplified Schematic Table of Contents 5 Revision History 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Timing Requirements 7.7 Switching Characteristics 7.8 Operating Characteristics 7.9 Typical Characteristics 8 Parameter Measurement Information 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Power Button Circuit 10.2.1 Design Requirements 10.2.2 Detailed Design Procedure 10.2.3 Application Curves 11 Power Supply Recommendations 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Trademarks 13.2 Electrostatic Discharge Caution 13.3 Glossary 14 Mechanical, Packaging, and Orderable Information
SCES794E – OCTOBER 2009 – REVISED JANUARY 2015
9 Detailed Description 9.1 Overview
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram 7 PRE 1 C CLK C C 5 Q TG C C C C 2 D TG TG TG 3 Q C C C 6 CLR 9.3 Feature Description
• Allow down voltage translation – 5 V to 3.3 V – 5.0 V to 1.8 V – 3.3 V to 1.8 V • Inputs accept voltage levels up to 5.5 V • Ioff Feature – Can prevent backflow current that can damage device when powered down
9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUTS PRE CLR CLK D Q Q
L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC1G74 Document Outline 1 Features 2 Applications 3 Description 4 Simplified Schematic Table of Contents 5 Revision History 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Timing Requirements 7.7 Switching Characteristics 7.8 Operating Characteristics 7.9 Typical Characteristics 8 Parameter Measurement Information 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Power Button Circuit 10.2.1 Design Requirements 10.2.2 Detailed Design Procedure 10.2.3 Application Curves 11 Power Supply Recommendations 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Trademarks 13.2 Electrostatic Discharge Caution 13.3 Glossary 14 Mechanical, Packaging, and Orderable Information