Datasheet AD9680 (Analog Devices) - 5

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Data Sheet AD9680 SPECIFICATIONS DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1. AD9680-500 AD9680-820 AD9680-1000 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −0.3 0 +0.3 −0.3 0 +0.3 −0.31 0 +0.31 % FSR Offset Matching Full 0 0.3 0 0.23 0 0.23 % FSR Gain Error Full −6 0 +6 −6 0 +6 −6 0 +6 % FSR Gain Matching Full 1 5.1 1 5.5 1 4.5 % FSR Differential Nonlinearity (DNL) Full −0.6 ±0.5 +0.7 −0.7 ±0.5 +0.8 −0.7 ±0.5 +0.8 LSB Integral Nonlinearity (INL) Full −4.5 ±2.5 +5.0 −3.3 ±2.5 +4.3 −5.7 ±2.5 +6.9 LSB TEMPERATURE DRIFT Offset Error Full −3 −10 −12 ppm/°C Gain Error Full ±25 ±54 ±13.8 ppm/°C INTERNAL VOLTAGE REFERENCE Voltage Full 1.0 1.0 1.0 V INPUT-REFERRED NOISE VREF = 1.0 V 25°C 2.06 2.46 2.63 LSB rms ANALOG INPUTS Differential Input Voltage Full 1.46 2.06 2.06 1.46 1.70 1.94 1.46 1.70 1.94 V p-p Range (Programmable) Common-Mode Voltage (VCM) 25°C 2.05 2.05 2.05 V Differential Input Capacitance1 25°C 1.5 1.5 1.5 pF Analog Input Full Power 25°C 2 2 2 GHz Bandwidth POWER SUPPLY AVDD1 Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V AVDD2 Full 2.44 2.50 2.56 2.44 2.50 2.56 2.44 2.50 2.56 V AVDD3 Full 3.2 3.3 3.4 3.2 3.3 3.4 3.2 3.3 3.4 V AVDD1_SR Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V DVDD Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V DRVDD Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V SPIVDD Full 1.7 1.8 3.4 1.7 1.8 3.4 1.7 1.8 3.4 V IAVDD1 Full 435 467 605 660 685 720 mA IAVDD2 Full 395 463 490 545 595 680 mA IAVDD3 Full 87 101 125 140 125 142 mA IAVDD1_SR Full 15 22 15 18 16 18 mA I 2 DVDD Full 145 152 205 246 208 269 mA I 1 DRVDD Full 190 237 200 240 200 225 mA IDRVDD (L = 2 mode) 25°C 140 N/A3 N/A3 mA ISPIVDD Full 5 6 5 6 5 6 mA Rev. B | Page 5 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE