Datasheet AD9680 (Analog Devices) - 26

AD9680 Data Sheet 80 0 7.0× SNR SFDR (dBc) 7.0× SFDR SFDR (dBFS) 8.0× SNR IMD3 (dBc) 75 8.0× SFDR –20 IMD3 (dBFS) ) S F ) B S 70 d –40 BF d AND Bc DR ( 65 –60 d F S 3 ( D NR/ S 60 /IM –80 R D SF 55 –100 50
4
–120 1010.3 1205.3 1410.3 1600.3 1810.3 1950.3
14
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
148 2-
ANALOG INPUT FREQUENCY (MHz)
75 1
INPUT AMPLITUDE (dBFS)
1752- 1 1 Figure 68. SNR/SFDR vs. fIN; 1 GHz < fIN < 2 GHz; Figure 71. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Buffer Control 1 (0x018) = 7.0× and 8.0× fIN1 = 184 MHz and fIN2 = 187 MHz
0 0 AIN1 AND AIN2 = –7dBFS SFDR (dBc) SFDR = 88dBFS SFDR (dBFS) IMD2 = 94dBFS IMD3 (dBc) –20 IMD3 = 88dBFS –20 IMD3 (dBFS) BUFFER CONTROL 1 = 2.0× ) S F ) B S –40 –40 F B d ND d ( A E c –60 B –60 UD d IT 3 ( L D P IM –80 –80 AM DR/ F S –100 –100 –120 –120–90 –81 –72 –63 –54 –45 –36 –27 –18 –9
149
0 50 100 150 200 250
-146
AMPLITUDE (dBFS)
1752-
FREQUENCY (MHz)
1 1752 1 Figure 69. Two-Tone FFT; f Figure 72. Two-Tone IMD3/SFDR vs. Input Amplitude (A IN1 = 184 MHz, fIN2 = 187 MHz IN) with fIN1 = 338 MHz and fIN2 = 341 MHz
0 110 AIN1 AND AIN2 = –7dBFS 100 SFDR = 88dBFS IMD2 = 88dBFS 90 –20 IMD3 = 89dBFS BUFFER CONTROL 1 = 4.5× ) 80 S F ) B 70 S –40 d 60 BF AND (d 50 E Bc –60 UD (d 40 IT R L D 30 P SF –80 AM 20 SNR/ 10 SFDR (dBFS) –100 0 SNR (dBFS) –10 SFDR (dBc) SNR (dBc) –20 –120 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
150 2-
0 50 100 150 200 250
-147
INPUT AMPLITUDE (dBFS)
175 1
FREQUENCY (MHz)
1752 1 Figure 70. Two-Tone FFT; f Figure 73. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz IN1 = 338 MHz, fIN2 = 341 MHz Rev. B | Page 26 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE