Datasheet TP65B110HRU (Renesas) - 6
| Hersteller | Renesas |
| Beschreibung | 650V 110mΩ High-Voltage GaN Bidirectional Switch in TOLT Package |
| Seiten / Seite | 15 / 6 — TP65B110HRU Datasheet. 2.7. Dynamic Characteristics. G2 On. G2 Off. … |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
TP65B110HRU Datasheet. 2.7. Dynamic Characteristics. G2 On. G2 Off. Symbol. Parameter. Test Conditions. (VG2S2 = 9V). (VG2S2 = 0V). Unit

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TP65B110HRU Datasheet 2.7 Dynamic Characteristics
TJ = 25°C, G1 blocking, unless otherwise stated.
G2 On G2 Off Symbol Parameter Test Conditions (VG2S2 = 9V) (VG2S2 = 0V) Unit Typical Typical
CISS Input Capacitance 810 777 VG1S1 = 0V COSS Output Capacitance VS2S1 = 400V 63 65 pF f = 1MHz CRSS Reverse Transfer Capacitance 0.9 0.7 CO(er) Output Capacitance, Energy Related [1] V 80 81 G1S1 = 0V V pF S2S1 = 0V to 400V CO(tr) Output Capacitance, Time Related [2] 156 134 V Q G1S1 = 0V OSS Output Charge VS2S1 = 0V to 400V 62 54 nC tD(on) Turn-on Delay 23.5 - VG1S1 = 0 to 9V tR Rise Time VS2S1 = 400 2.6 - IS2S1 = 5A ns tD(off) Turn-off Delay Rg,on = 27Ω 19.2 - Rg,off = 3.3Ω tF Fall Time 15.4 - 1. Equivalent capacitance to give same stored energy from 0V to 400V. 2. Equivalent capacitance to give same charging time from 0V to 400V.
2.8 Diode Characteristics
TJ = 25°C unless otherwise stated.
Symbol Parameter [1] Test Conditions Minimum Typical Maximum Unit
G1 off (VG1S1 = 0V) VSS,FW Free-Wheeling Voltage Drop G2 on (VG2S2 = 9V) - 1.9 - V IS1S2 = 10A 1. Negligible reverse recovery charge due to low-voltage Silicon MOSFET technology. R07DS1683EU0100 Rev.1.00 Page 6 Mar 10, 2026 Document Outline 1. Pin Information 1.1 Pin Assignments 1.2 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Specifications 2.3 Recommended Operating Conditions 2.4 Gate Characteristics 2.5 On-State Characteristics 2.6 Off-State Characteristics 2.7 Dynamic Characteristics 2.8 Diode Characteristics 3. Typical Characteristics 4. Test Circuits and Waveforms 5. Modes of Operation 6. Device Architecture 7. Design Considerations 8. Package Outline Drawings 9. Related Information 10. Ordering Information 11. Revision History