Datasheet EPC23108 (Efficient Power Conversion) - 8

eGaN® IC DATASHEET
EPC23109
Application Information
where Max T
General Description
J is specified at 125 °C and the ambient temperature is specified at 25 °C. The big variable in achieving the theoretical maximum The EPC23109 ePowerTM Stage IC integrates a half-bridge gate driver power dissipation is RθJA, the thermal resistance from junction to ambient. with internal high-side and low-side FETs. Integration is implemented The EPC23109 package construction al ows two paral el paths of heat using EPC’s proprietary GaN IC technology. The monolithic chip dissipation where the bottom path goes from junction to metal ization integrates input logic interface, level shifting, bootstrap charging and to lead-frame then the exposed pads at the bottom of the package. gate drive buffer circuits control ing high-side and low-side eGaN RθJB_bottom is determined by the three power bars (VIN, SW and PGND) output FETs configured as a half-bridge power stage. Robust level which are designed to al ow maximum contact area to the underlying shifters from low-side to high-side channels are designed to operate PCB pads. The total thermal resistance to ambient in this path of correctly with soft and hard switching conditions even at large negative RθJA_bottom needs to add the heat dissipation from the PCB pads clamped voltage and to avoid false trigger from fast dv/dt transients through the multi-layer PCB construction then radiating to the ambient including those driven by external sources or other phases. Internal which is highly dependent on the airflow and forced cooling method. circuits integrate the functions of charging and disabling of the logic (See Figure 9). and bootstrap power supplies. Protection features are added to protect the output FETs
Figure 7: Functional Block Diagram
from unwanted turn-on at low or even complete loss of supply voltages. The single chip GaN IC is C mounted inside a 3.5 x 5 mm Quad Flat No-lead DD 4 (QFN) package using a flip chip on lead-frame VDD 5 V
High-side
V 13 technique. This packaging structure al ows DRV BOOT R R BOOT very low parasitic inductance from the power C UVLO BOOT 12 DRV Shutdown VIN Sync terminals to the underlying PCB solder pads. logic boot VIN 10 CBOOT The exposed QFN pads are designed to have Level Gate at least 0.6 mm spacing between high and low Logic driver C shift IN 65 kΩ + voltage pins to meet IPC voltage creepage rule 3 DT VPHASE 11 SD/STB for 100 V. Another enhancement exposes the + POR 9 backside of the GaN IC die on the top side of SW + the package while completely encapsulating 2 EN Cross- V R DD DRV 6 over V the rest of the GaN IC die. This al ows a very low DRV Delay 1 PWM LO match Gate R thermal resistance path from the die junction to DRV level driver an attached heatsink which in effect increases shift 7 AGND PGND 8 the al owable power dissipation and thus higher current handling capability.
Output Current Rating
Power stage output current rating is best thought of as a figure
Figure 8: EPC23109 QFN package outline, pinouts and exposed
of merit for specified output current level that accounts for the
backside of the GaN IC die
maximum amount of power dissipation al owed from the IC. Total power dissipation from a power stage IC is tied to the application 10 circuit topologies, output current demand, switching frequencies,
Bottom
9 construction, operating temperature range, thermal management technique and mechanical stress limit of the metal ization imposed 8 11 by electromigration. The rating is related to the respective maximum 1213 current capability of the two integrated output FETs in the half-bridge
Top
power stage but not measured the same way as individual discrete FET. For a power stage IC such as EPC23109, total power loss from the IC is 1 2 7 the sum of the two output FETs conduction, switching and deadtime
23109 A
3
YYYY
6 4 losses imposed by the application topologies at operating switching
ZZZZ
5 frequencies as well as power losses from the gate drive and logic circuit. The maximum power dissipation is defined by the fol owing formula:
Max P
Lot_Date Code Line 1 Lot_Date Code Line 2
Diss = (Max TJ - TA) / RθJA
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