Datasheet LTC7890 (Analog Devices) - 7

HerstellerAnalog Devices
BeschreibungLow IQ, Dual, 2-Phase Synchronous Step-Down Controller for GaN FETs in 40-Lead QFN (6mm x 6mm, Plastic Side Wettable) package
Seiten / Seite41 / 7 — LTC7890. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. Figure 3. Pin …
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LTC7890. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. Figure 3. Pin Configuration. Table 3. Pin Function Descriptions. Pin No

LTC7890 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3 Pin Configuration Table 3 Pin Function Descriptions Pin No

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LTC7890 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 FREQ Frequency Control Pin for the Internal Voltage Controlled Oscillator (VCO). Connect FREQ to GND for a fixed frequency of 370 kHz. Connect FREQ to INTVCC for a fixed frequency of 2.25 MHz. Program frequencies between 100 kHz and 3 MHz by using a resistor between FREQ and GND. Minimize the capacitance on FREQ. 2 MODE Mode Select Input. This input determines how the LTC7890 operates at light loads. Connect MODE to GND to select Burst Mode® operation. An internal 100 kΩ resistor to GND also invokes Burst Mode operation when MODE is floating. Connect MODE to INTVCC to force continuous inductor current operation. Tying MODE to INTVCC through a 100 kΩ resistor selects the pulse skipping operation. 3 PLLIN/SPREAD External Synchronization Input to Phase Detector/Spread Spectrum Enable. When an external clock is applied to PLLIN/SPREAD, the PLL forces the rising TGxx1 signal to synchronize with the rising edge of the external clock. When not synchronizing to an external clock, tie this input to INTVCC to enable spread spectrum dithering of the oscillator, or to GND to disable spread spectrum dithering. 4 RUN1 Run Control Input for Channel 1. Forcing RUN1 less than 1.08 V disables controller switching. Forcing RUN1 and RUN2 less than 0.7 V shuts down the LTC7890, reducing IQ to approximately 1 µA. Tie the RUN1 pin to VIN for always on operation. 5 RUN2 Run Control Input for Channel 2. Forcing RUN2 less than 1.08 V disables controller switching. Forcing RUN1 and RUN2 less than 0.7 V shuts down the LTC7890, reducing IQ to approximately 1 µA. Tie the RUN2 pin to VIN for always on operation. 6 GND Ground. The GND pin and the exposed pad must be soldered to PCB ground for rated electrical and thermal performance. 7 DRVUV DRVCC UVLO and EXTVCC Switchover Program Pin. DRVUV determines the INTVCC UVLO and EXTVCC switchover rising and falling thresholds, as listed in Table 1. 8 DRVSET INTVCC Regulation Program Pin. DRVSET sets the regulation point for the INTVCC LDO linear regulators. Connect DRVSET to GND to set INTVCC to 5 V. Connect DRVSET to INTVCC to set INTVCC to 5.5 V. Program voltages between 4 V and 5.5 V by placing a resistor (50 kΩ to 110 kΩ) between DRVSET and GND. The resistor and an internal 20 µA source current create a voltage used by the INTVCC LDO regulator to set the regulation point. 9 DTCA Dead Time Control Pin for Bottom FET Off to Top FET On Delay. Connect DTCA to GND to program an adaptive dead time delay of approximately 20 ns. Connect DTCA to INTVCC to program a smart near zero delay between BGUPx falling and SWx rising. Connect a 10 kΩ to 200 kΩ resistor between DTCA and GND to add additional delay (from 7 ns to 60 ns) between BGUPx falling and SWx rising. This setting applies to both channels. 10 DTCB Dead Time Control Pin for Top FET Off to Bottom FET On Delay. Connect DTCB to GND to program an adaptive dead time delay of approximately 20 ns. Connect DTCB to INTVCC to program a smart near zero delay between SWx falling and BGDNx rising. Connect a 10 kΩ to 200 kΩ resistor between DTCB and GND to add additional delay (from 7 ns to 60 ns) between SWx falling and BGDNx rising. This setting applies to both channels. 11 SENSE2− Negative Input to the Differential Current Comparator for Channel 2. The SENSE2− pin supplies current to the current comparator of Channel 2 when SENSE2– is greater than INTVCC. 12 SENSE2+ Positive Input to the Differential Current Comparator for Channel 2. The ITH2 pin voltage and controlled offset between the SENSE2− and SENSE2+ pins, in conjunction with the current sense resistor (RSENSE), set the current trip threshold.
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Document Outline Features Applications Typical Application Circuit General Description Specifications Electrical Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Functional Diagram Main Control Loop Power and Bias Supplies (VIN, EXTVCC, DRVCC, and INTVCC) High-Side Bootstrap Capacitor Dead Time Control (DTCA and DTCB Pins) Startup and Shutdown (RUNx and TRACK/SSx Pins) Light Load Operation: Burst Mode Operation, Pulse Skipping Mode, or Forced Continuous Mode (MODE Pin) Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and PLLIN/SPREAD Pins) Output Overvoltage Protection Foldback Current Power-Good Applications Information Inductor Value Calculation Inductor Core Selection Current Sense Selection Low Value Resistor Current Sensing Inductor DCR Current Sensing Setting the Operating Frequency Selecting the Light Load Operating Mode Dead Time Control (DTCA and DTCB Pins) DTCx Pins Tied to GND (Adaptive Dead Time Control) DTCx Pins Tied to INTVCC (Smart Near Zero Dead Time Control) DTCx Pins Connected with a Resistor to GND Power FET Selection CIN and COUT Selection Setting the Output Voltage RUNx Pins and Undervoltage Lockout Soft Start and Tracking (TRACK/SSx Pin) 2-Phase Single Output Operation INTVCC Regulators (OPTI-DRIVE) Topside FET Driver Supply (CB) Minimum On-Time Considerations Fault Conditions: Current Limit and Foldback Fault Conditions: Overvoltage Protection Fault Conditions: Overtemperature Protection Phase-Locked Loop and Frequency Synchronization Efficiency Considerations Checking Transient Response Design Example PCB Layout Checklist PCB Layout Debugging Typical Applications Related Products Outline Dimensions Ordering Guide Evaluation Boards