Datasheet A4988 (Allegro) - 9

DMOS Microstepping Driver A4988 with Translator and Overcurrent Protection
tion of current flow in each winding. The size of the increment is ▪ ROSC through a resistor to ground — off-time is determined determined by the combined state of the MSx inputs. by the following formula; the decay mode is automatic Mixed for all step modes except full-step which is set to Slow.
Direction Input (DIR).
This determines the direction of rota- t tion of the motor. Changes to this input do not take effect until the OFF ≈ ROSC ⁄ 825 next STEP rising edge. where tOFF is in µs.
Blanking.
This function blanks the output of the current sense
Internal PWM Current Control.
Each full-bridge is con- comparators when the outputs are switched by the internal current trolled by a fixed off-time PWM current control circuit that limits control circuitry. The comparator outputs are blanked to prevent the load current to a desired value, ITRIP . Initially, a diagonal pair false overcurrent detection due to reverse recovery currents of the of source and sink FET outputs are enabled and current flows clamp diodes, and switching transients related to the capacitance through the motor winding and the current sense resistor, RSx. of the load. The blank time, tBLANK (µs), is approximately When the voltage across RSx equals the DAC output voltage, the tBLANK ≈ 1 µs current sense comparator resets the PWM latch. The latch then turns off the appropriate source driver and initiates a fixed off-
Shorted Load and Short-to-Ground Protection.
time decay mode If the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the The maximum value of current limiting is set by the selection of overcurrent event and disabling the driver that is shorted, protect- RSx and the voltage at the VREF pin. The transconductance func- ing the device from damage. In the case of a short-to-ground, the tion is approximated by the maximum value of current limiting, device will remain disabled (latched) until the S¯ ¯L ¯E ¯E ¯P input goes ITripMAX (A), which is set by high or VDD power is removed. A short-to-ground overcurrent event is shown in Figure 4. ITripMAX = VREF / ( 8 × RS) When the two outputs are shorted together, the current path is where R through the sense resistor. After the blanking time (≈1 µs) expires, S is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. This causes the driver to go into The DAC output reduces the VREF output to the current sense a fixed off-time cycle. After the fixed off-time expires, the driver comparator in precise steps, such that turns on again and the process repeats. In this condition, the driver is completely protected against overcurrent events, but the Itrip = (%ITripMAX / 100) × ITripMAX short is repetitive with a period equal to the fixed off-time of the driver. This condition is shown in Figure 5. (See Table 2 for %ITripMAX at each step.) During a shorted load event, it is normal to observe both a posi- It is critical that the maximum rating (0.5 V) on the SENSE1 and tive and negative current spike as shown in Figure 3, due to the SENSE2 pins is not exceeded. direction change implemented by the Mixed decay feature. This is shown in Figure 6. In both instances, the overcurrent circuitry is
Fixed Off-Time.
The internal PWM current control circuitry protecting the driver and prevents damage to the device. uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The off-time, t
Charge Pump (CP1 and CP2).
The charge pump is used OFF, is determined by the ROSC terminal. The ROSC terminal has three settings: to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 µF ceramic capacitor should be ▪ ROSC tied to VDD — off-time internally set to 30 µs; decay connected between CP1 and CP2. In addition, a 0.1 µF ceramic mode is automatic Mixed, except when in full-step where capacitor is required between VCP and VBB, to act as a reservoir decay mode is set to Slow. for operating the high-side FET gates. ▪ ROSC tied directly to ground — off-time internally set to Capacitor values should be Class 2 dielectric ±15% maximum, 30 µs; current decay is set to Mixed for both increasing and or tolerance R, according to EIA (Electronic Industries Alliance) decreasing currents for all step modes. specifications. 9 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com