Datasheet IP101G (IC Plus) - 2
| Hersteller | IC Plus |
| Beschreibung | Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver |
| Seiten / Seite | 66 / 2 — Table Of Contents |
| Dateiformat / Größe | PDF / 1.7 Mb |
| Dokumentensprache | Englisch |
Table Of Contents
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Table Of Contents
Table Of Contents.. 2 List of Figures .. 4 List of Tables.. 5 Revision History... 6 Features comparison between IP101G and IP101A/IP101AH ... 7 Transmit and Receive Data Path Block Diagram .. 8 1 Pin diagram .. 9 2 Dice pad information ...11 3 Pin description.. 12 3.1 IP101GA pin description .. 12 3.2 IP101GR/GRI pin description... 16 4 Register Descriptions ... 19 4.1 Register Page mode Control Register ... 20 4.2 MII Registers.. 20 4.3 MMD Control Register ... 30 4.4 MMD Data Register ... 31 4.5 RX Counter Register.. 34 4.6 LED Pin Control Register... 35 4.7 WOL+ Control Register.. 35 4.8 UTP PHY Specific Control Register ... 38 4.9 Digital IO Pin Control Register ... 39 5 Function Description... 41 5.1 Major Functional Block Description ... 41 5.1.1 Transmission Description.. 41 5.1.2 MII and Management Control Interface .. 42 5.1.3 RMII Interface ... 43 5.1.4 Flexible Clock Source ... 45 5.1.5 Auto-Negotiation and Related Information.. 45 5.1.6 Auto-MDIX function... 46 5.2 PHY Address Configuration ... 46 5.3 Power Management Tool ... 48 5.3.1 Auto Power Saving Mode ... 48 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) ... 49 5.3.3 Force power down .. 49 5.3.4 WOL+ operation mode.. 49 5.4 LED Mode Configuration.. 53 5.5 LED Blink Timing.. 53 5.6 Repeater Mode .. 53 5.7 Interrupt.. 53 5.8 Miscellaneous .. 53 5.9 Serial Management Interface... 54 5.10 Fiber Mode Setting... 55 5.11 Jumbo Frame... 55 6 Layout Guideline .. 56 6.1 General Layout Guideline .. 56 6.2 Twisted Pair recommendation.. 56 7 Electrical Characteristics.. 57 7.1 Absolute Maximum Rating ... 57 7.2 DC Characteristics ... 57 7.3 Crystal Specifications... 58 2/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN
Table Of Contents
Table Of Contents.. 2 List of Figures .. 4 List of Tables.. 5 Revision History... 6 Features comparison between IP101G and IP101A/IP101AH ... 7 Transmit and Receive Data Path Block Diagram .. 8 1 Pin diagram .. 9 2 Dice pad information ...11 3 Pin description.. 12 3.1 IP101GA pin description .. 12 3.2 IP101GR/GRI pin description... 16 4 Register Descriptions ... 19 4.1 Register Page mode Control Register ... 20 4.2 MII Registers.. 20 4.3 MMD Control Register ... 30 4.4 MMD Data Register ... 31 4.5 RX Counter Register.. 34 4.6 LED Pin Control Register... 35 4.7 WOL+ Control Register.. 35 4.8 UTP PHY Specific Control Register ... 38 4.9 Digital IO Pin Control Register ... 39 5 Function Description... 41 5.1 Major Functional Block Description ... 41 5.1.1 Transmission Description.. 41 5.1.2 MII and Management Control Interface .. 42 5.1.3 RMII Interface ... 43 5.1.4 Flexible Clock Source ... 45 5.1.5 Auto-Negotiation and Related Information.. 45 5.1.6 Auto-MDIX function... 46 5.2 PHY Address Configuration ... 46 5.3 Power Management Tool ... 48 5.3.1 Auto Power Saving Mode ... 48 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) ... 49 5.3.3 Force power down .. 49 5.3.4 WOL+ operation mode.. 49 5.4 LED Mode Configuration.. 53 5.5 LED Blink Timing.. 53 5.6 Repeater Mode .. 53 5.7 Interrupt.. 53 5.8 Miscellaneous .. 53 5.9 Serial Management Interface... 54 5.10 Fiber Mode Setting... 55 5.11 Jumbo Frame... 55 6 Layout Guideline .. 56 6.1 General Layout Guideline .. 56 6.2 Twisted Pair recommendation.. 56 7 Electrical Characteristics.. 57 7.1 Absolute Maximum Rating ... 57 7.2 DC Characteristics ... 57 7.3 Crystal Specifications... 58 2/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN