Datasheet SR6P3EC4 (STMicroelectronics) - 6
| Hersteller | STMicroelectronics |
| Beschreibung | 32-bit Arm Cortex R52+ automotive integration MCU 4 Cortex R52+ cores, 19.5 MB xMemory, 1.8 MB RAM, with embedded virtualization, safety, and security in FPBGA292 package |
| Seiten / Seite | 10 / 6 — SR6P3EC4 SR6P3EC6. Ordering information. Table 2. Ordering information … |
| Dateiformat / Größe | PDF / 572 Kb |
| Dokumentensprache | Englisch |
SR6P3EC4 SR6P3EC6. Ordering information. Table 2. Ordering information scheme. Device family. Serie / line. Package. Memory size
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Textversion des Dokuments
SR6P3EC4 SR6P3EC6 Ordering information 2 Ordering information Table 2. Ordering information scheme
Example: SR6 P3E C6 XM C5FX 0 R
Device family
SR6: "Stellar" SR6 family
Serie / line
P3E: SR6 P series, P3E line
Package
C4: FPBGA292 C6: FPBGA476
Memory size
XM: xMemory configuration, extensible from 10 MB to 19.5 MB 92: 10 MB fixed memory configuration 96: 14 MB fixed memory configuration
Device options
C5FX: default, without 10BASE-T1S C5EX: with 10BASE-T1S Others: reserved
Reserved Packing
Y: Tray R: Tape and reel (pin 1 top right)
DB5468
-
Rev 4 page 6/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN
Example: SR6 P3E C6 XM C5FX 0 R
Device family
SR6: "Stellar" SR6 family
Serie / line
P3E: SR6 P series, P3E line
Package
C4: FPBGA292 C6: FPBGA476
Memory size
XM: xMemory configuration, extensible from 10 MB to 19.5 MB 92: 10 MB fixed memory configuration 96: 14 MB fixed memory configuration
Device options
C5FX: default, without 10BASE-T1S C5EX: with 10BASE-T1S Others: reserved
Reserved Packing
Y: Tray R: Tape and reel (pin 1 top right)
DB5468
-
Rev 4 page 6/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN