Datasheet AP3917D (Diodes) - 9

AP3917D Performance Characteristics
(continued)
Overload Protection (OLP)
With the increase of the load, the peak current and switching frequency increase. When the load continues to increase, peak current reaches its maximum limitation, and the OFF time is at its minimum, the output voltage and FB voltage will decrease. When the FB voltage drops below OLP threshold VFB_OLP (1.7V), the internal overload timer will start to count. Once the overload duration lasts more than the OLP delay time tOLP (170ms), OLP occurs. The OLP’s time delay setting should avoid triggering the OLP when the system starts up or enters a load transition phase. Therefore, it is required that the system startup time must be less than tOLP. The 170ms time delay of tOLP is calculated under the condition of 36kHz operating frequency. Different operating frequencies correspond to different time delays. The time delay calculation under different operating frequencies ( f ) is as follows: S 36kHz D t ELAY  170ms  ( ) fS
Short-Circuit Protection (SCP)
The AP3917D shuts down when the peak current exceeds short-circuit threshold, and the AP3917D resumes operation when the fault is removed.
Over-Temperature Protection (OTP)
The AP3917D integrates an internal over-temperature protection function. The AP3917D shuts down when the inner junction temperature exceeds thermal shutdown threshold TOTP (+150°C). After exceeding the threshold, the BP voltage begins to drop. When the BP voltage drops to VBP_RESTART (4.5V), the internal high-voltage regulator turns on to charge the external BP capacitor.
Open-Loop Detection
When the FB voltage drops below open-loop detection threshold voltage VOLD (60mV), the AP3917D stops working and begins a restart cycle. The open-loop detection is blanked for 64 switching cycles during startup process.
Overshoot Improvement
In general, there is no capacitor between FB pin and S pin. But in some cases where strict overshoot is required, we recommend a ceramic capacitor C6 (390pF to 1nF) in Figure 6. R1 D2 C4 C5 R2 R3 C6 L2 BP S +V FB S NC Drain NC U1 AP3917D Figure 6. Overshoot Improvement
Leading-Edge Blanking
A narrow spike on the leading edge of the current waveform can usually be observed when the power MOSFET is turned on. Normally, the leading-edge blanking time tLEB1 is built in to prevent the false-triggering caused by the turn-on spike. But in the case of short circuit, the leading- edge blanking time is tLEB2. During this period, the current limit comparator is disabled, and the gate driver cannot be switched off. AP3917D 9 of 12 March 2025 Document number: DS41540 Rev. 8 - 3
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