Datasheet MAX5048 (Analog Devices) - 8

MAX5048 7.6A, 12ns, SOT23/TDFN, MOSFET Driver
IN+ VIH VIL P_OUT AND N_OUT TIED 90% TOGETHER 10% tD–OFF tF tD–ON tR TIMING DIAGRAM V+ V+ MAX5048A MAX5048B IN+ P_OUT INPUT N_OUT OUTPUT IN- GND CL TEST CIRCUIT Figure 1. Timing Diagram and Test Circuit The quiescent current is 0.95mA typical. The current • Place one or more 0.1µF decoupling ceramic capaci- required to charge and discharge the internal nodes is tor(s) from V+ to GND as close to the device as possi- frequency dependent (see the Typical Operating ble. At least one storage capacitor of 10µF (min) Characteristics). The MAX5048A/MAX5048B power dis- should be located on the PC board with a low resis- sipation when driving a ground referenced resistive tance path to the V+ pin of the MAX5048A/MAX5048B. load is: • There are two AC current loops formed between the P = D x RON(MAX) x ILOAD2 device and the gate of the MOSFET being driven. where D is the fraction of the period the MAX5048A/ The MOSFET looks like a large capacitance from MAX5048Bs’ output pulls high, R gate to source when the gate is being pulled low. ON (MAX) is the maxi- mum on-resistance of the device with the output high The active current loop is from N_OUT of the (P-channel), and I MAX5048A/MAX5048B to the MOSFET gate to the LOAD is the output load current of the MAX5048A/MAX5048B. MOSFET source and to GND of the MAX5048A/ MAX5048B. When the gate of the MOSFET is being For capacitive loads, the power dissipation is: pulled high, the active current loop is from P_OUT of P = CLOAD x (V+)2 x FREQ the MAX5048A/MAX5048B to the MOSFET gate to where C the MOSFET source to the GND terminal of the LOAD is the capacitive load, V+ is the supply voltage, and FREQ is the switching frequency. decoupling capacitor to the V+ terminal of the decoupling capacitor and to the V+ terminal of the
Layout Information
MAX5048A/MAX5048B. While the charging current The MOSFET drivers MAX5048A/MAX5048B source- loop is important, the discharging current loop is crit- and-sink large currents to create very fast rise and fall ical. It is important to minimize the physical distance edges at the gate of the switching MOSFET. The high and the impedance in these AC current paths. di/dt can cause unacceptable ringing if the trace • In a multilayer PCB, the component surface layer lengths and impedances are not well controlled. The surrounding the MAX5048A/MAX5048B should con- following PCB layout guidelines are recommended sist of a GND plane containing the discharging and when designing with the MAX5048A/MAX5048B: charging current loops. 8 Maxim Integrated