Datasheet LAN8022 (Microchip) - 9

LAN8022 2.2 Pin Descriptions
This section contains descriptions of the various LAN8022 pins. The “
_N
” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example,
RESET_N
indicates that the reset signal is active low. When “
_N
” is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac- tive.
TABLE 2-3: PIN DESCRIPTIONS Name Symbol Buffer Type Description Ethernet (Line Interface)
Ethernet Line
RXIN0N
AI Negative input signal of Port 0 dif erential pair. Port 0 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Negative input termination.
Note:
External AC coupling is required and is typical y built into the SFP module. Ethernet Line
RXIN0P
AI Positive input signal of Port 0 dif erential pair. Port 0 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Positive input termination.
Note:
External AC coupling is required and is typical y built into the SFP module. Ethernet Line
RXIN1N
AI Negative input signal of Port 1 dif erential pair. Port 1 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Negative input termination.
Note:
External AC coupling is required and is typical y built into the SFP module. Ethernet Line
RXIN1P
AI Positive input signal of Port 1 dif erential pair. Port 1 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Positive input termination.
Note:
External AC coupling is required and is typical y built into the SFP module. Ethernet Line
TXOUT0N
AO Negative output signal of Port 0 dif erential pair. Port 0 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Negative output termination.
Note:
External AC coupling is required and is typical y built into the SFP module. Ethernet Line
TXOUT0P
AO Positive output signal of Port 0 dif erential pair. Port 0 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Positive output termination.
Note:
External AC coupling is required and is typical y built into the SFP module.  2025 Microchip Technology Inc. and its subsidiaries DS00006160B-page 9 Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 MACsec 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 MAC 3.2.8 Flow Control Buffer 3.2.9 MACsec 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 MACsec Operation 3.7.1 MACsec Crypto 3.7.2 MACsec Capture FIFO 3.7.3 Debug Fault Code in CRC 3.7.4 MACsec Frame Encapsulations and Transforms 3.7.5 MACsec Host Formats 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 Recovered Clock Timing Requirements 4.6.8 Reset Pin Configuration Strap Timing 4.6.9 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support